发明公开
EP1229462A1 Method and apparatus for analysing a source current waveform in a semiconductor integrated circuit
有权
一种用于在半导体集成电路分析的源极电流的波形的方法和装置
- 专利标题: Method and apparatus for analysing a source current waveform in a semiconductor integrated circuit
- 专利标题(中): 一种用于在半导体集成电路分析的源极电流的波形的方法和装置
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申请号: EP01126335.7申请日: 2001-11-06
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公开(公告)号: EP1229462A1公开(公告)日: 2002-08-07
- 发明人: Nagata, Makoto , Iwata, Atsushi
- 申请人: Semiconductor Technology Academic Research Center
- 申请人地址: 3-17-2, Shin Yokohama, Kohoku-ku Yokohama-shi, Kanagawa 222-0033 JP
- 专利权人: Semiconductor Technology Academic Research Center
- 当前专利权人: Semiconductor Technology Academic Research Center
- 当前专利权人地址: 3-17-2, Shin Yokohama, Kohoku-ku Yokohama-shi, Kanagawa 222-0033 JP
- 代理机构: Prüfer, Lutz H., Dipl.-Phys.
- 优先权: JP2001026795 20010202
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G01R31/30 ; G01R31/3167
摘要:
The invention provides a method of analyzing a source current at a higher speed and an enhanced accuracy in a semiconductor integrated circuit including a digital circuit. The method to analyze a waveform of the source current, with consideration of re-distribution of charges throughout the digital circuit in the semiconductor integrated circuit, expressing the digital circuit with series of parasitic capacitors ΣC ch,↑ (nT) and ΣC ch,↓ (nT) to be charged and connected between the source and the ground lines. The capacitor series are calculated in time series based on the distribution of switching operations of the logic gates included in the digital circuit. An analysis model for determining the waveform of the source current in the digital circuit is obtained by connecting the parasitic capacitor series with a couple of respective parasitic impedances Z d and Z g of the source line and the ground line.
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