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31 条记录 (耗时 0.019 秒)

    Method and apparatus for analysing a source current waveform in a semiconductor integrated circuit
    2.
    发明公开
    Method and apparatus for analysing a source current waveform in a semiconductor integrated circuit 有权
    一种用于在半导体集成电路分析的源极电流的波形的方法和装置

    公开(公告)号：EP1229462A1

    公开(公告)日：2002-08-07

    申请号：EP01126335.7

    申请日：2001-11-06

    申请人： Semiconductor Technology Academic Research Center

    发明人： Nagata, Makoto ,  Iwata, Atsushi

    IPC分类号： G06F17/50 ,  G01R31/30 ,  G01R31/3167

    CPC分类号： G06F17/5036 ,  G01R31/3004

    摘要： The invention provides a method of analyzing a source current at a higher speed and an enhanced accuracy in a semiconductor integrated circuit including a digital circuit. The method to analyze a waveform of the source current, with consideration of re-distribution of charges throughout the digital circuit in the semiconductor integrated circuit, expressing the digital circuit with series of parasitic capacitors ΣC ch,↑ (nT) and ΣC ch,↓ (nT) to be charged and connected between the source and the ground lines. The capacitor series are calculated in time series based on the distribution of switching operations of the logic gates included in the digital circuit. An analysis model for determining the waveform of the source current in the digital circuit is obtained by connecting the parasitic capacitor series with a couple of respective parasitic impedances Z d and Z g of the source line and the ground line.

    摘要翻译： 本发明提供了以较高的速度和在半导体集成电路包括数字电路精度提高分析的源极电流的方法。 的方法来分析源电流的波形，并考虑的电荷重新分布在整个半导体集成电路的数字电路的，表达数字电路具有串联寄生电容SIGMA Cch中＆uarr＆（* nT）和SIGMA Cch中＆darr＆ （NT）被充电和连接在源极和接地线之间。 电容器串联在时间序列基础上的转换包括在所述数字电路栅极上的逻辑的动作的分布计算。 确定性采矿在数字电路中的源极电流的波形的分析模型由寄生电容器串联一对夫妇respectivement寄生阻抗ZD和源极线的ZG和接地线的连接得到。

    Computing circuit, computing apparatus, and semiconductor computing circuit
    3.
    发明公开
    Computing circuit, computing apparatus, and semiconductor computing circuit 审中-公开
    Rechenschaltung，Recheneinrichtung und Halbleiter-Rechenschaltung

    公开(公告)号：EP1076310A1

    公开(公告)日：2001-02-14

    申请号：EP00305956.5

    申请日：2000-07-13

    申请人： Semiconductor Technology Academic Research Center

    发明人： Shibata, Tadashi ,  Konda, Masahiro ,  Ohmi, Tadahiro

    IPC分类号： G06G7/14

    CPC分类号： G11C11/5621 ,  G06G7/14 ,  G11C27/005 ,  H04N19/94

    摘要： Disclosed are a computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences, and a semiconductor computing circuit achievable with simple circuitry and suitable for use in such a computing circuit or apparatus. The computing circuit capable of computing the absolute difference comprises a large input selection circuit 1 which outputs either a first signal or a second signal whichever is larger, a small input selection circuit 2 which outputs either the first and second signals whichever signal is smaller, and a subtraction circuit 3 which subtracts the output of the small input selection circuit 2 from the output of the large input selection circuit 1. The subtraction circuit 3 comprises a capacitor 6, a first switch 4 provided between a first terminal of the capacitor 6 and the output of the large input selection circuit 1, a second switch 5 provided between the first terminal of the capacitor 6 and the output of the small input selection circuit 2, and a third switch 7 provided between a second terminal of the capacitor 6 and a terminal connected to a prescribed potential. The computing apparatus capable of computing the sum of absolute differences comprises a plurality of such computing circuits, and computes the sum of the outputs of the computing circuits by using a summing circuit.

    摘要翻译： 公开了一种能够计算与高速模拟计算的绝对差异的计算电路，能够计算绝对差的和的计算装置以及适用于这种计算电路或装置的简单电路可实现的半导体计算电路 。 能够计算绝对差的计算电路包括大输入选择电路1，其输出第一信号或第二信号（较大者），小输入选择电路2，输出第一和第二信号，无论信号较小者，以及 减法电路3，其从大输入选择电路1的输出中减去小输入选择电路2的输出。减法电路3包括电容器6，设置在电容器6的第一端和第一开关4之间的第一开关4， 大输入选择电路1的输出，设置在电容器6的第一端和小输入选择电路2的输出之间的第二开关5，以及设置在电容器6的第二端子与端子之间的第三开关7 连接到规定的电位。 能够计算绝对差的和的计算装置包括多个这样的计算电路，并且通过使用求和电路来计算计算电路的输出之和。

    Ferroelectric non-volatile memory device
    4.
    发明公开
    Ferroelectric non-volatile memory device 有权
    非易失性铁电存储器阵列

    公开(公告)号：EP1054406A3

    公开(公告)日：2001-01-17

    申请号：EP00109433.3

    申请日：2000-05-03

    申请人： Semiconductor Technology Academic Research Center

    发明人： Ishiwara, Hiroshi

    IPC分类号： G11C11/22 ,  G11C27/02

    CPC分类号： G11C11/22 ,  G11C11/223

    摘要： A ferroelectric non-volatile memory device comprising a MOS cell transistor (Q1), two ferroelectric capacitors (C A , C B ) each of which has one terminal connected to the gate electrode of the cell transistor (Q1) and has almost the same remanent polarization, and a selector transistor (Q2) connected to the other terminal of one ferroelectric capacitor C B , wherein data is stored by polarizing the ferroelectric thin films of the capacitors in opposite directions with respect to the gate electrode of the cell transistor (Q1).

    Ferroelectric non-volatile memory device
    5.
    发明公开
    Ferroelectric non-volatile memory device 有权
    说唱歌手Nichtflüchtigeferroelektrische Speicherannnung

    公开(公告)号：EP1054406A2

    公开(公告)日：2000-11-22

    申请号：EP00109433.3

    申请日：2000-05-03

    申请人： Semiconductor Technology Academic Research Center

    发明人： Ishiwara, Hiroshi

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  G11C11/223

    摘要： A ferroelectric non-volatile memory device comprising a MOS cell transistor (Q1), two ferroelectric capacitors (C A , C B ) each of which has one terminal connected to the gate electrode of the cell transistor (Q1) and has almost the same remanent polarization, and a selector transistor (Q2) connected to the other terminal of one ferroelectric capacitor C B , wherein data is stored by polarizing the ferroelectric thin films of the capacitors in opposite directions with respect to the gate electrode of the cell transistor (Q1).

    摘要翻译： 一种铁电非易失性存储器件，包括MOS单元晶体管（Q1），两个铁电电容器（CA，CB），每个具有一个端子连接到单元晶体管（Q1）的栅电极并具有几乎相同的剩余极化， 以及连接到一个强电介质电容器CB的另一个端子的选择晶体管（Q2），其中通过相对于单元晶体管（Q1）的栅电极在相反方向使电容器的铁电薄膜偏振来存储数据。

    Ferroelectric non-volatile memory device
    9.
    发明公开
    Ferroelectric non-volatile memory device 审中-公开
    说唱歌手Nichtflüchtigeferroelektrische Speicherannnung

    公开(公告)号：EP1473736A2

    公开(公告)日：2004-11-03

    申请号：EP04017770.1

    申请日：2000-05-03

    申请人： Semiconductor Technology Academic Research Center

    发明人： Ishiwara, Hiroshi

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  G11C11/223

    摘要： A ferroelectric non-volatile memory device comprising a MOS cell transistor (Q1), two ferroelectric capacitors (C A , C B ) each of which has one terminal connected to the gate electrode of the cell transistor (Q1) and has almost the same remanent polarization, and a selector transistor (Q2) connected to the other terminal of one ferroelectric capacitor C B , wherein data is stored by polarizing the ferroelectric thin films of the capacitors in opposite directions with respect to the gate electrode of the cell transistor (Q1).

    摘要翻译： 一种铁电非易失性存储器件，包括MOS单元晶体管（Q1），两个铁电电容器（CA，CB），每个具有一个端子连接到单元晶体管（Q1）的栅电极并具有几乎相同的剩余极化， 以及连接到一个强电介质电容器CB的另一个端子的选择晶体管（Q2），其中通过相对于单元晶体管（Q1）的栅电极在相反方向使电容器的铁电薄膜偏振来存储数据。

    Sampling and hold circuit
    10.
    发明公开
    Sampling and hold circuit 有权
    Abtast- und Halteschaltung

    公开(公告)号：EP1315172A1

    公开(公告)日：2003-05-28

    申请号：EP02025821.6

    申请日：2002-11-18

    申请人： Semiconductor Technology Academic Research Center

    发明人： Kawahito, Shoji ,  Miyazaki, Daisuke

    IPC分类号： G11C27/02

    CPC分类号： G11C27/026

    摘要： A sampling and hold circuit that can suppress voltage variation at the input terminals, which are virtual grounds, of a differential amplifier, depending on the frequency of input signals. During sampling operation, a serial circuit composed of a capacitor C1, to which a positive-side input voltage ViP is applied, and an NMOS transistor Q4, which is always turned on, is connected to an input terminal INP of a differential amplifier circuit 2. A serial circuit having the same impedance as that serial circuit and composed of a capacitor C3, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q9 is also connected to the input terminal INP. A serial circuit composed of a capacitor C2, to which a negative-side input voltage ViM is applied, and an NMOS transistor Q5, which is always turned on, is connected to the other input terminal INM of a differential amplifier circuit 2. A serial circuit having the same impedance as that serial circuit and composed of a capacitor C4, to which a positive-side input voltage ViP is applied, and an NMOS transistor Q10 is also connected to the input terminal INM.

    摘要翻译： 采样和保持电路，可根据输入信号的频率，抑制差分放大器的虚拟接地输入端的电压变化。 在采样操作期间，由施加有正侧输入电压ViP的电容器C1和始终导通的NMOS晶体管Q4构成的串联电路连接到差分放大电路2的输入端INP 具有与串联电路相同的阻抗并由施加有负侧输入电压ViM的电容器C3和NMOS晶体管Q9组成的串联电路也连接到输入端子INP。 由施加了负侧输入电压ViM的电容器C2和始终导通的NMOS晶体管Q5构成的串联电路连接到差分放大电路2的另一输入端INM。串行 具有与该串联电路相同的阻抗并且由施加了正侧输入电压ViP的电容器C4组成的电路以及NMOS晶体管Q10也连接到输入端子INM。