Apparatus and method for reducing sampling circuit timing mismatch

Invention Grant

EP2775481B1 Apparatus and method for reducing sampling circuit timing mismatch 有权

Title translation: 装置和方法用于降低采样电路的时间失配

Patent Title: Apparatus and method for reducing sampling circuit timing mismatch
Patent Title (中): 装置和方法用于降低采样电路的时间失配
Application No.: EP14156535.8

Application Date: 2014-02-25
Publication No.: EP2775481B1

Publication Date: 2016-05-04
Inventor: Singer, Lawrence A. , Devarajan, Siddharth
Applicant: Analog Devices, Inc.
Applicant Address: One Technology Way Norwood, MA 02062-9106 US
Assignee: Analog Devices, Inc.
Current Assignee: Analog Devices, Inc.
Current Assignee Address: One Technology Way Norwood, MA 02062-9106 US
Agency: Thompson, Andrew John
Priority: US201361774432P 20130307; US201313975291 20130824
Main IPC: G11C27/02
IPC: G11C27/02 ; H03M1/08 ; H03M1/12 ; H03K17/041

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