公开(公告)号：EP2779451B1

公开(公告)日：2017-10-18

申请号：EP14159383.0

申请日：2014-03-13

Applicant: Analog Devices, Inc.

Inventor： Devarajan, Siddharth ,  Singer, Lawrence A.

IPC: H03K17/0412 ,  G11C27/02

CPC classification number: H03K17/04 ,  G11C27/02 ,  H03K17/04123 ,  H03K2217/0054

公开(公告)号：EP2775481A2

公开(公告)日：2014-09-10

申请号：EP14156535.8

申请日：2014-02-25

Applicant: Analog Devices, Inc.

Inventor： Singer, Lawrence A. ,  Devarajan, Siddharth

IPC: G11C27/02

CPC classification number: H03M1/1245 ,  G11C27/02 ,  G11C27/024 ,  H03K17/041 ,  H03M1/0836 ,  H03M1/1215

Abstract: An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.

Abstract translation: 的示例性装置，系统和方法，用于在具有多个信道交织的采样电路采样英寸 ，实施例中，以输入时钟用于取样时钟的转变从第一到第二电压电平，相对于彼此同步。 采样时钟被输入到采样电路。 输入时钟开关的公共开关确实拉各采样时钟到所述第二电压电平通过在输入时钟转变到第二时钟状态的公共路径从第一。 从第一到每个采样时钟的第二电压电平的转变触发的信道之一所取的样品。 第一电压电平可以被提升到上驱动开关在采样电路。 通过公共开关和公共路径同步的输出的过渡降低取样时钟控制信道之间的时序不匹配。

公开(公告)号：EP3021489A1

公开(公告)日：2016-05-18

申请号：EP15194532.6

申请日：2015-11-13

Applicant: Analog Devices, Inc.

Inventor： Devarajan, Siddharth ,  Singer, Lawrence ,  Shrestha, Prawal Man ,  Huang, Pingli

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/10

CPC classification number: H03M1/121 ,  H03M1/00 ,  H03M1/0604 ,  H03M1/0607 ,  H03M1/0609 ,  H03M1/0612 ,  H03M1/066 ,  H03M1/0836 ,  H03M1/1033 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/124

Abstract: A time-interleaved analog-to-digital converter (ADC) uses M sub-analog-to-digital converters (sub-ADCs) to, according to a sequence, sample an analog input signal to produce digital outputs. When the M sub-ADCs are interleaved, the digital outputs exhibit mismatch errors between the M sub-ADCs due to mismatches between the sub-ADCs. A more second order subtle effect is that the mismatch error for a particular digital output from a particular ADC, due to internal coupling or other such interaction and effects between the M sub-ADCs, can vary depending on which sub-ADC(s) were used before and/or after the particular sub-ADC. If M sub-ADCs are time-interleaved randomly, the mismatches between the M sub-ADCs become a function of the sub-ADC selection pattern in the sequence. The present disclosure describes mechanisms for measuring and reducing these order-dependent mismatches to achieve high dynamic range performance in the time-interleaved ADC.

Abstract translation: 时间交错模拟数字转换器（ADC）使用M个子模拟 - 数字转换器（子ADC），其中，根据一个序列，采样模拟输入信号以产生数字输出。 当M个子ADC被交错，所述M个子ADC之间由于子ADC之间的失配的数字输出呈现的失配误差。 更二阶微妙效果做了失配误差从特定ADC特定数字输出，由于内部耦合或其他搜索相互作用和M个子ADC之间效果可以变化，这取决于子ADC（S）是 之前和/或所述特定子ADC后使用。 如果M个子ADC是时间交织随机地，将所述M个子ADC之间的失配变得序列中的子ADC选择模式的功能。 本公开描述了用于测量和减少合成顺序依赖性的失配，以实现在时间交织ADC的高动态范围的性能的机制。

公开(公告)号：EP2779451A1

公开(公告)日：2014-09-17

申请号：EP14159383.0

申请日：2014-03-13

Applicant: Analog Devices, Inc.

Inventor： Devarajan, Siddharth ,  Singer, Lawrence A.

IPC: H03K17/0412 ,  G11C27/02

CPC classification number: H03K17/04 ,  G11C27/02 ,  H03K17/04123 ,  H03K2217/0054

Abstract: An apparatus and method for implementing a bootstrapped switching circuit (100) having improved (i.e. faster) turn-on time is provided. In an embodiment, an inner switching loop (mn1x, C BOOTX , mp0x) is implemented in a bootstrapped switching circuit where the inner switching loop is configured to turn on an input switch (mn1, mn1x) in the bootstrapped drive circuit independent of the drive circuit output (qbtstrp). The embodiment decouples the inner switching loop circuitry from the output drive circuit of the bootstrapped switching circuit (mn1, C BOOT , MP0), which typically has a larger load capacitance than the inner switching loop. This allows the inner switching loop to turn on the input switch in the bootstrapped switching circuit faster and decreases the turn-on time of the bootstrapped switching circuit.

Abstract translation: 提供了一种用于实现具有改进（即更快）导通时间的自举开关电路（100）的装置和方法。 在一个实施例中，内部开关环路（mn1x，C BOOTX，mp0x）被实现在自举交换电路中，其中内部开关环路被配置为接通独立于驱动器的自举驱动电路中的输入开关（mn1，mn1x） 电路输出（qbtstrp）。 该实施例将内部开关回路电路与自举开关电路（mn1，C BOOT，MP0）的输出驱动电路分离，其通常具有比内部开关环路更大的负载电容。 这允许内部开关环路更快地接通自举开关电路中的输入开关，并降低自举开关电路的接通时间。

公开(公告)号：EP2779449A2

公开(公告)日：2014-09-17

申请号：EP14157068.9

申请日：2014-02-27

Applicant: Analog Devices, Inc.

Inventor： Devarajan, Siddharth ,  Singer, Lawrence

IPC: H03H19/00

CPC classification number: H03K5/01 ,  H03H19/006 ,  H03H19/008 ,  H03K2217/0018

Abstract: In one example embodiment, a programmable capacitor array (300) is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry (110) to switch on and off an array of MOSFET switches. The control circuitry (110) turns on a MOSFET (104) to load a capacitance (C1) on Vin and turns off the MOSFET (104) to remove the capacitance (C1) from Vin in response to a Din control signal. When the intention is to load the capacitance (C1) with Vin, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance (C1) from Vin, the MOSFET (104) is primarily turned off, however, the MOSFET (104) is still periodically turned on with appropriate voltage levels in response to a clock signal (CLK) for periods of time when the loading of the capacitance (C1) on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system.

Abstract translation: 在一个示例性实施例中，通过利用控制电路（110）接通和关断MOSFET开关阵列，提供可编程电容器阵列（300）以实现低失真并最小化输入（Vin）的线性度退化。 响应于Din控制信号，控制电路（110）接通MOSFET（104）以在Vin上加载电容（C1）并关断MOSFET（104）以从Vin去除电容（C1）。 当意图用Vin加载电容（C1）时，MOSFET会持续保持导通状态。 当意图从Vin移除或卸载电容（C1）时，MOSFET（104）主要关断，然而，MOSFET（104）仍然响应于时钟信号（CLK）以适当的电压电平周期性地导通 ）在Vin上的电容（C1）的加载对于系统是可容忍的时间段内，由此确保由于可编程电容器阵列系统导致的Vin的最小线性劣化。

公开(公告)号：EP2779449B1

公开(公告)日：2016-11-30

申请号：EP14157068.9

申请日：2014-02-27

Applicant: Analog Devices, Inc.

Inventor： Devarajan, Siddharth ,  Singer, Lawrence

IPC: H03H19/00

CPC classification number: H03K5/01 ,  H03H19/006 ,  H03H19/008 ,  H03K2217/0018

公开(公告)号：EP2775481B1

公开(公告)日：2016-05-04

申请号：EP14156535.8

申请日：2014-02-25

Applicant: Analog Devices, Inc.

Inventor： Singer, Lawrence A. ,  Devarajan, Siddharth

IPC: G11C27/02 ,  H03M1/08 ,  H03M1/12 ,  H03K17/041

CPC classification number: H03M1/1245 ,  G11C27/02 ,  G11C27/024 ,  H03K17/041 ,  H03M1/0836 ,  H03M1/1215

公开(公告)号：EP2775481A3

公开(公告)日：2015-03-18

申请号：EP14156535.8

申请日：2014-02-25

Applicant: Analog Devices, Inc.

Inventor： Singer, Lawrence A. ,  Devarajan, Siddharth

IPC: G11C27/02 ,  H03M1/08 ,  H03M1/12 ,  H03K17/041

CPC classification number: H03M1/1245 ,  G11C27/02 ,  G11C27/024 ,  H03K17/041 ,  H03M1/0836 ,  H03M1/1215

Abstract: An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.

公开(公告)号：EP2779449A3

公开(公告)日：2014-10-08

申请号：EP14157068.9

申请日：2014-02-27

Applicant: Analog Devices, Inc.

Inventor： Devarajan, Siddharth ,  Singer, Lawrence

IPC: H03H19/00

CPC classification number: H03K5/01 ,  H03H19/006 ,  H03H19/008 ,  H03K2217/0018

Abstract: In one example embodiment, a programmable capacitor array (300) is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry (110) to switch on and off an array of MOSFET switches. The control circuitry (110) turns on a MOSFET (104) to load a capacitance (C1) on Vin and turns off the MOSFET (104) to remove the capacitance (C1) from Vin in response to a Din control signal. When the intention is to load the capacitance (C1) with Vin, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance (C1) from Vin, the MOSFET (104) is primarily turned off, however, the MOSFET (104) is still periodically turned on with appropriate voltage levels in response to a clock signal (CLK) for periods of time when the loading of the capacitance (C1) on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system.