A hardware secure element is described. The hardware secure element comprises a microprocessor (106a) and a memory (108), such as a non-volatile memory, having stored a plurality of software routines (HI, H2) executable by the microprocessor (106a), wherein each software routine (HI, H2) starts at a respective memory start address. The hardware secure element comprises also a receiver circuit configured to receive data comprising a command (CMD), and a hardware message handler module (316). The hardware message handler module (316) determines a software routine (HI, H2) to be executed by the microprocessor (106a) as a function of the command (CMD), and provides data (ADDR) to the microprocessor (106a) indicating the software routine to be executed.