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公开(公告)号：EP4064100A1
公开(公告)日：2022-09-28
申请号：EP22161788.9
申请日：2022-03-14
IPC分类号： G06F21/76
摘要： A processing system (10a) is described. The processing system (10a) comprises a microprocessor (1020), a hardware circuit (110) configured to change operation as a function of decoded life-cycle data (LC) and a non-volatile memory (104) configured to stored encoded life-cycle data (LCD). A hardware configuration circuit (108) is configured to read the encoded life-cycle data (LCD) from the non-volatile memory (104), decode the encoded life-cycle data (LCD) and provide the decoded life-cycle data (LC) to the hardware circuit (110). The processing system comprises also a reset circuit (116) configured to monitor an external reset signal received via a reset terminal (RP) and, in response to determining that the external reset signal has a first logic level, execute a reset phase (3002), a configuration phase (CP1) and a wait phase (3022), where the reset circuit (116) waits until the external reset signal has a second logic level.
In particular, the processing system comprises also a communication interface (IF_JTAG) activated during the wait phase (3022) and configured to receive a request (REQ), and a hardware verification circuit (130) configured to generate a life-cycle advancement request signal (LCFA_REQ) when the request (REQ) comprises a given reference password (RK) and the reset circuit (116) is in the wait phase (3022). A write circuit (1044w) of the non-volatile memory (104) may thus write one or more bits of the encoded life-cycle data (LCD) stored in the non-volatile memory (104) when the life-cycle advancement request signal (LCFA_REQ) is set, thereby advancing the life-cycle to a given predetermined life-cycle stage.-
公开(公告)号：EP3404573A1
公开(公告)日：2018-11-21
申请号：EP18171177.1
申请日：2018-05-08
CPC分类号： G06F21/83 , G06F9/3816 , G06F9/445 , G06F12/02 , G06F21/57 , G06F21/64 , G06F21/74 , G06F2212/7209 , H04L9/3234 , H04L63/0853
摘要： A hardware secure element is described. The hardware secure element comprises a processing unit and a receiver circuit configured to receive data comprising a command field (CMD) and a parameter field (P) adapted to contain a plurality of parameters.
The hardware secure element comprises also at least one hardware parameter check module (318) configured to receive at input a parameter to be processed (P(P_ID)) selected from said plurality of parameters, and process said parameter to be processed (P(P ID)) in order to verify whether said parameter (P(P_ID)) has given characteristics.
The hardware parameter check module (318) has associated one or more look-up tables (302c; 302d, 302e) configured to receive at input said command field (CMD) and a parameter index (P_ID) identifying said parameter to be processed (P(P_ID)) by said hardware parameter check module (318), and determine for said command field (CMD) and said parameter index (P_ID) a configuration data element (CDE), said configuration data element (CDE) comprising configuration information specifying the characteristics to be verified by said hardware parameter check module (318).-
3.发明公开
公开(公告)号：EP4187415A1
公开(公告)日：2023-05-31
申请号：EP22205161.7
申请日：2022-11-02
申请人： STMicroelectronics Application GmbH , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
摘要： A processing system (10a) is described. The processing system (10a) comprises a plurality of storage elements (113), wherein each storage element (113) is configured to receive a write request comprising a data bit (DATA) and store the received data bit (DATA) to a latch or flip-flop (1122). A hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation as a function of the logic level stored to the latch or flip-flop (1122) of a first storage element (113) of the plurality of storage elements (113). A non-volatile memory (104; 126) is configured to store data bits (CD, LCD) for the plurality of storage elements (113) and a hardware configuration circuit (108) is configured to read the data bits from the non-volatile memory (104; 126) and generate write requests in order to store the data bits to the storage elements (113).
Specifically, the hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation also as a function of the first tamper signal (TAMP). For this purpose, the first storage element (113) comprises a further latch or flip-flop (1124) and is configured to store, in response to the write request, the inverted version (1126) of the received data bit to the further latch or flip-flop (1124). The first storage element (113) comprises also a combinational logic circuit (1128) configured to compare the logic level stored to the latch or flip-flop (1122) of the first storage element (113) with the logic level stored to the further latch or flip-flop (1122) of the first storage element (113). The combinational logic circuit (1128) is configured to de-assert a first tamper signal (TAMP) associated with the first storage element (113) when the logic levels are different, and assert the first tamper signal (TAMP) when the logic levels are the same.-
4.发明公开
公开(公告)号：EP3401826A2
公开(公告)日：2018-11-14
申请号：EP18171148.2
申请日：2018-05-08
IPC分类号： G06F21/57 , G06F21/60 , G06F21/77 , H03K19/177
CPC分类号： G06F21/71 , G06F11/0721 , G06F11/0751 , G06F11/0772 , G06F21/57 , G06F21/602 , G06F21/72 , G06F21/77 , H03K19/17728 , H04L9/0618 , H04L2209/12 , H04L2209/127
摘要： A hardware secure element is described. The hardware secure element comprises a microprocessor (106a) and a memory (108), such as a non-volatile memory, having stored a plurality of software routines (HI, H2) executable by the microprocessor (106a), wherein each software routine (HI, H2) starts at a respective memory start address. The hardware secure element comprises also a receiver circuit configured to receive data comprising a command (CMD), and a hardware message handler module (316). The hardware message handler module (316) determines a software routine (HI, H2) to be executed by the microprocessor (106a) as a function of the command (CMD), and provides data (ADDR) to the microprocessor (106a) indicating the software routine to be executed.
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公开(公告)号：EP4064001A1
公开(公告)日：2022-09-28
申请号：EP22162915.7
申请日：2022-03-18
摘要： A processing system (10a) is described. The processing system comprises a microprocessor, a reset circuit (116a), a non-volatile memory having stored configuration data, a plurality of configuration data clients (112) and a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data to the configuration data clients (112). In response to switching on the processing system (10a), the processing system (10a) executes a reset phase (DR), a configuration phase (CP1) and a software runtime phase (SW).
In particular, the processing system (10a) comprises a first reset terminal (RPa) having associated a first circuitry (30a, 32a) and a second reset terminal (RPb) having associated a first circuitry (30a, 32a), wherein the first circuitry (30a, 32a) and the second circuitry (30b, 32b) have associated at least one configuration data client (112a, 112b), and wherein the configuration data comprise first mode configuration data (MCDa) for the first terminal (RPa) and second mode configuration data (MCDb) for the second terminal (RPb).
During the reset phase (DR) and the configuration phase (CP1) the first circuitry (30a, 32a) activates a strong pull-down resistance, and the second circuitry (30b, 32b) activate a weak pull-down resistance. Conversely, once the configuration phase is completed, and in particular during the software runtime phase (SW), the first circuitry (30a, 32a) may activate a weak pull-down resistance, e.g., for implementing a bi-direction reset terminal, or a weak pull-up resistance, e.g., for implementing a reset output terminal. Conversely, the second circuitry (30b, 32b) may activate a weak or strong pull-up resistance, e.g., for implementing a reset output terminal, or maintain activated the weak pull-down resistance, e.g., for implementing a reset input terminal.-
公开(公告)号：EP3992646A1
公开(公告)日：2022-05-04
申请号：EP21202658.7
申请日：2021-10-14
申请人： STMicroelectronics International N.V. , STMicroelectronics Application GmbH , STMicroelectronics S.r.l.
IPC分类号： G01R31/317 , G06F1/04 , G06F11/16 , G06F11/273 , G11C7/22
摘要： A testing tool (10) includes a clock generation circuit (16, 18, 22) generating a test clock (Tck) and outputting the test clock via a test clock output pad (31), data processing circuitry (19) clocked by the test clock, and data output circuitry (20) receiving data output from the data processing circuitry and outputting the data via an input/output, IO pad (32), the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit (41) generating a delayed version of the test clock (DELAYED_TCK), and data input circuitry (21) receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock (DELAYED_TCK). The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer (50) and receipt of the data input from the external computer via the IO pad.
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公开(公告)号：EP3401183B1
公开(公告)日：2020-04-22
申请号：EP18171268.8
申请日：2018-05-08
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8.发明公开
公开(公告)号：EP3401826A3
公开(公告)日：2019-02-13
申请号：EP18171148.2
申请日：2018-05-08
IPC分类号： G06F21/57 , G06F21/60 , G06F21/77 , H03K19/177
摘要： A hardware secure element is described. The hardware secure element comprises a microprocessor (106a) and a memory (108), such as a non-volatile memory, having stored a plurality of software routines (HI, H2) executable by the microprocessor (106a), wherein each software routine (HI, H2) starts at a respective memory start address. The hardware secure element comprises also a receiver circuit configured to receive data comprising a command (CMD), and a hardware message handler module (316). The hardware message handler module (316) determines a software routine (HI, H2) to be executed by the microprocessor (106a) as a function of the command (CMD), and provides data (ADDR) to the microprocessor (106a) indicating the software routine to be executed.
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公开(公告)号：EP3401183A1
公开(公告)日：2018-11-14
申请号：EP18171268.8
申请日：2018-05-08
摘要： A processing system (10a) is described. The processing system (10a) comprises at least one hardware block configured to change operation as a function of configuration data (CD), a non-volatile memory (104) comprising the configuration data (CD) for the at least one hardware block, and configuration means (108, 112) configured to read the configuration data (CD) from the non-volatile memory (104) and provide the configuration data (CD) read from the non-volatile memory (104) to the at least one hardware block.
The configuration means (108, 112) are configured to:
- receive mode configuration data (MDU);
- read the configuration data (CD) from the non-volatile memory (104);
- test whether the configuration data (CD) contain errors by verifying whether the configuration data (CD) are corrupted and/or invalid;
- in case the configuration data (CD) do not contain errors, activating a normal operation mode of the processing system (10a) by providing the configuration data (CD) read from the non-volatile memory (104) to the at least one hardware block (110); and
- in case the configuration data (CD) do contain errors, activating an error operation mode of the processing system (10a) as a function of the mode configuration data (MDU) by:
- providing reset values (120) to the at least one hardware block (110) when the mode configuration data (MDU) indicate that a reset mode should be activated; and
- providing preset configuration data (122) to the at least one hardware block (110) when the mode configuration data (MDU) indicate that a degraded mode should be activated.
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