-
公开(公告)号：EP4373038A1
公开(公告)日：2024-05-22
申请号：EP23207659.6
申请日：2023-11-03
Inventor： DONDINI, Mirko , TRECARICHI, Calogero Andrea , RENNIG, Fred
IPC: H04L12/40
CPC classification number: H04L12/40006 , H04L2012/4021520130101 , H04L2012/4027320130101
Abstract: A processing system (10a) is described. The processing system (10a) comprises a processing circuit (64), a volatile memory (60a) and a CAN communication controller circuit (50). The CAN communication controller circuit (50) comprises configuration and status registers (520). A transmission handler circuit (502) and a reception handler circuit (504) are configured to transmit and receive data via the CAN core circuit (500) by exchanging data with the volatile memory (60a) based on the configuration data stored to the configuration and status registers (520), and standard and/or extended filter elements stored to the volatile memory (60a).
Specifically, the processing system (10a) further comprises a hardware host circuit (62a) comprising a non-volatile memory (642) configured to store first configuration data (CD1) and second configuration data (CD2), wherein the first configuration data (CD1) comprise configuration data to be transferred to the configuration and status registers (520) of the CAN communication controller circuit (50) and the second configuration data (CD2) comprise at least one standard and/or extended filter element to be transferred to the volatile memory (60a). A control circuit (620, 628, 632) is configured to manage an initialization mode, a reception mode and a transmission mode. Specifically, during the initialization mode (648), the hardware host circuit (62a) stores the first configuration data (CD1) to the configuration and status registers (520) and the second configuration data (CD2) to the volatile memory (60a).-
2.发明公开
公开(公告)号：EP4319064A1
公开(公告)日：2024-02-07
申请号：EP23185507.3
申请日：2023-07-14
Applicant: STMicroelectronics Application GmbH
Inventor： RENNIG, Fred
IPC: H04L12/40 , H04L61/5038 , H04L41/08
Abstract: An electronic device (42) includes a CAN protocol controller (320), a first communication port (326d) configured for coupling to a first segment of a differential bus to exchange CAN signals therewith, and a second communication port (326u) configured for coupling to a second segment of the differential bus to exchange CAN signals therewith. A first CAN transceiver circuit (324d) is coupled to the CAN protocol controller (320) and is configured to receive a first CAN transmission signal ( TXDd ) therefrom and to transmit a first CAN reception signal ( RXDd ) thereto. The first CAN transceiver circuit (324d) is coupled to the first communication port (326d) to drive (50) a differential voltage at the first segment of the differential bus as a function of the first CAN transmission signal ( TXDd ) and to sense (56) a differential voltage at the first segment of the differential bus to produce the first CAN reception signal ( RXDd ) . The second communication port (326u) is enabled in response to a control signal ( DISABLE ) being de-asserted and disabled in response to the control signal ( DISABLE ) being asserted. The CAN signals are passed between the first communication port (326d) and the second communication port (326u) in response to the control signal ( DISABLE ) being de-asserted, and the CAN signals are not passed between the first communication port (326d) and the second communication port (326u) in response to the control signal ( DISABLE ) being asserted.
-
公开(公告)号：EP4174692A1
公开(公告)日：2023-05-03
申请号：EP22201273.4
申请日：2022-10-13
Inventor： GOYAL, Avneep Kumar , SZURMANT, Thomas
Abstract: A system on a chip including a first-port controller (106) for a first development port (102) configured to receive a first development tool and a second-port controller (108) for a second development port (104) configured to receive a second development tool. The system on a chip further including a central controller (110) in communication with the first-port controller (106), the second-port controller (108), and a security subsystem (112). The central controller (110) being configured to manage authentication exchanges between the security subsystem (112) and the first development tool and authentication exchanges between the security subsystem (112) and the second development tool.
-
公开(公告)号：EP4141677A1
公开(公告)日：2023-03-01
申请号：EP22192295.8
申请日：2022-08-26
Inventor： SHARMA, Vivek Mohan , COLOMBO, Roberto
Abstract: A processing system is described. The processing system comprises an error detection circuit (46) configured to receive data bits (DATA) and ECC bits. The error detection circuit (46) calculates further ECC bits as a function of the data bits (DATA) and generates a syndrome (SYN) by comparing the calculated ECC bits with the received ECC bits. When the syndrome (SYN) corresponds to one of N + K single bit-flip reference syndromes, the error detection circuit (46) asserts a first error signal (ERR 1 ), and asserts one bit of a bit-flip signature (SIG) corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
The processing system further comprises a test circuit (48) configured to provide, during a test-mode (TM), a sequence of patterns (PAT) to the error detection circuit (46), each pattern (PAT) comprising data bits (DATA) and ECC bits. Specifically, the test circuit (48) obtains a first pattern (PAT) without ECC errors, provides the first pattern (PAT) to the error detection circuit (46) and verifies whether the first error signal (ERR 1 ) is de-asserted and all bits of the bit-flip signature (SIG) are de-asserted. Moreover, the test circuit (48) obtains a sequence of N + K further bit-flip signatures (FSIG), each further bit-flip signature (SIG) having asserted a single bit. Moreover, the test circuit obtains (1008, 1014) for each further bit-flip signature (FSIG) a respective second pattern (PAT), wherein each second pattern (PAT) corresponds to a pattern having a single bit flipped with respect to a reference pattern at the positions of the single asserted bit of the respective further bit-flip signature (FSIG). The test circuit provides each second pattern (PAT) to the error detection circuit (46) and verifies whether the first error signal (ERR 1 ) is asserted and the bit-flip signature (SIG) corresponds to the respective further bit-flip signature.-
公开(公告)号：EP4105785A1
公开(公告)日：2022-12-21
申请号：EP22176130.7
申请日：2022-05-30
Inventor： CAVALLARO, Giuseppe , RENNIG, Fred
Abstract: A microcontroller (80) comprises a processing unit and a deserial-serial peripheral interface module (81'). The deserial-serial peripheral interface module is configured to be coupled to a communication bus (84) which operates according to a selected communication protocol. The processing unit is configured to read user data intended for inclusion in an outgoing frame encoded according to the selected communication protocol. The processing unit is further configured to calculate, as a function of the user data, a CRC value intended for inclusion in the outgoing frame. The processing unit is further configured to compose the outgoing frame including the user data and the calculated CRC value into the outgoing frame. The processing unit is further configured to produce a DSPI frame encoded according to the selected communication protocol as a function of the outgoing frame. The processing unit is further configured to program a data register of the deserial-serial peripheral interface module (81') with the DSPI frame. Operation of the deserial-serial peripheral interface module (81') results in transmission of the DSPI frame via the communication bus (84).
-
Patent Agency Ranking
公开(公告)号：EP4068101A1
公开(公告)日：2022-10-05
申请号：EP22163832.3
申请日：2022-03-23
Inventor： COLOMBO, Roberto , SHARMA, Vivek Mohan
IPC: G06F11/27 , G06F11/25 , G06F11/30 , G01R31/317 , G06F11/22
Abstract: A processing system (10a) is described. The processing system comprises a plurality of safety monitoring circuits (SM) configured to generate a plurality of error signals (ERR; ERR') by monitoring the operation of a processing core (102), a memory controller (100) and/or a resource (106). A fault collection and error management circuit (1206) receives the plurality of error signals (ERR; ERR') and generates one or more reaction signals.
In particular, the processing system comprises also a hardware connectivity test circuit (1208, 1210) configured to test the connectivity between the plurality of safety monitoring circuits (SM) and the fault collection and error management circuit (1206). The connectivity test circuit (1208, 1210) comprises for each error signal (ERR') a circuit (1208, SL, CL) configured to selectively assert or de-assert the respective error signal (ERR') generated by a respective safety monitoring circuit (SM) as a function of a respective selection signal (SE, CE). A control circuit (1210) sets the selection signals (SE, CE) in order to de-assert a first subset of the error signals (ERR') via the circuit (1208, SL, CL) and determines whether the respective error signals (ERR') of the first subset received by the fault collection and error management circuit (1206) are de-asserted. Similarly, the control circuit (1210) sets the selection signals (SE, CE) in order to assert a second subset of the error signals (ERR') via the circuit (1208, SL, CL) and determines whether the respective error signals (ERR') of the second subset received by the fault collection and error management circuit (1206) are asserted.-
公开(公告)号：EP4064794A2
公开(公告)日：2022-09-28
申请号：EP22305278.8
申请日：2022-03-11
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics Application GmbH
Inventor： GAERTNER, Manuel , SIRITO-OLIVIER, Philippe , TORRISI, Giovanni Luca , URBITSCH, Thomas , ROUSSEL, Christophe , BURKHARDT, Fritz
IPC: H05B45/37 , H05B45/325 , H05B45/10 , H05B45/46 , H05B45/52 , H05B47/25 , H02M3/335 , B60Q11/00 , B60Q1/14
Abstract: A system (100') comprises a microcontroller unit (102) and a driver device (101) coupled (105) to the microcontroller unit (102) to receive data therefrom. The driver device (101) comprises a plurality of output supply pins (101C 1 , ..., 101C n ) and is configured to selectively propagate (30 1 , ..., 30 n ) a supply voltage ( V BAT ) to the output supply pins (101C 1 , ..., 101C n ) to provide respective pulse-width modulated supply signals ( V BAT,1 , ..., V BAT,n ) at the output supply pins (101C 1 , ..., 101C n ). The driver device (101) is configured to compute respective duty-cycle values of the pulse-width modulated supply signals ( V BAT,1 , ..., V BAT,n ) as a function of the data received from the microcontroller unit (102) . The system further comprises a plurality of lighting devices (31 1,1 , ..., 31 1,m , 31 n ) coupled to the plurality of output supply pins (101C 1 , ..., 101C n ). The plurality of lighting devices (31 1,1 , ..., 31 1,m , 31 n ) comprises at least one subset of lighting devices (31 1,1 , ..., 31 1,m ) coupled to a same output supply pin (101C 1 ) in the plurality of output supply pins (101C 1 , ..., 101C n ). The system further comprises a set of respective electronic switches coupled in series to the lighting devices in the at least one subset of lighting devices (31 1,1 , ..., 31 1,m ). The microcontroller unit (102) is configured to individually control the electronic switches via respective control signals ( P 1,1 , ..., P 1,m ) to individually adjust a brightness of the lighting devices in the at least one subset of lighting devices (31 1,1 , ..., 31 1,m ).
-
公开(公告)号：EP4064100A1
公开(公告)日：2022-09-28
申请号：EP22161788.9
申请日：2022-03-14
IPC: G06F21/76
Abstract: A processing system (10a) is described. The processing system (10a) comprises a microprocessor (1020), a hardware circuit (110) configured to change operation as a function of decoded life-cycle data (LC) and a non-volatile memory (104) configured to stored encoded life-cycle data (LCD). A hardware configuration circuit (108) is configured to read the encoded life-cycle data (LCD) from the non-volatile memory (104), decode the encoded life-cycle data (LCD) and provide the decoded life-cycle data (LC) to the hardware circuit (110). The processing system comprises also a reset circuit (116) configured to monitor an external reset signal received via a reset terminal (RP) and, in response to determining that the external reset signal has a first logic level, execute a reset phase (3002), a configuration phase (CP1) and a wait phase (3022), where the reset circuit (116) waits until the external reset signal has a second logic level.
In particular, the processing system comprises also a communication interface (IF_JTAG) activated during the wait phase (3022) and configured to receive a request (REQ), and a hardware verification circuit (130) configured to generate a life-cycle advancement request signal (LCFA_REQ) when the request (REQ) comprises a given reference password (RK) and the reset circuit (116) is in the wait phase (3022). A write circuit (1044w) of the non-volatile memory (104) may thus write one or more bits of the encoded life-cycle data (LCD) stored in the non-volatile memory (104) when the life-cycle advancement request signal (LCFA_REQ) is set, thereby advancing the life-cycle to a given predetermined life-cycle stage.-
公开(公告)号：EP3432190B1
公开(公告)日：2020-09-23
申请号：EP18182223.0
申请日：2018-07-06
Applicant: STMicroelectronics Application GmbH
Inventor： COLOMBO, Mr. Roberto
-
10.发明授权
公开(公告)号：EP3425552B1
公开(公告)日：2020-09-02
申请号：EP18178541.1
申请日：2018-06-19
Inventor： COLOMBO, Roberto , BERTONI, Guido Marco , ORLANDO, William , VITTIMANI, Roberta
-
-
-
-
-
-
-
-
-
Search Results
72
records
(took 0.026 seconds)
