公开(公告)号：EP4249928B1

公开(公告)日：2024-08-14

申请号：EP23160225.1

申请日：2023-03-06

IPC分类号： G01R31/3185

CPC分类号： G01R31/318552 ,  G01R31/318558 ,  G01R31/318594 ,  G01R31/318544

公开(公告)号：EP4216222B1

公开(公告)日：2024-06-19

申请号：EP22211620.4

申请日：2022-12-06

IPC分类号： G11C29/32 ,  G11C29/12 ,  G11C29/48

CPC分类号： G11C29/1201 ,  G11C29/48 ,  G11C29/32

公开(公告)号：EP4339628A1

公开(公告)日：2024-03-20

申请号：EP23194464.6

申请日：2023-08-31

申请人： STMicroelectronics S.r.l.

发明人： NICOLLINI, Germano ,  VAIANA, Michele

IPC分类号： G01R27/26

摘要： A measurement system is described. The measurement system comprises a first capacitance (C 1 ), a second capacitance (C 2 ), a switching circuit (32a), a control circuit (36a) and a measurement circuit (34a). During a normal operating phase, the measurement system charges and discharges the first and second capacitances. For this purpose, the switching circuit (32a) and the control circuit (36a) periodically connect a first terminal of the first capacitance (C 1 ) to a first voltage (V 1 ) and a reference voltage (V ref ), and similarly a first terminal of the second capacitance (C 2 ) to a second voltage (V 2 ) and the reference voltage (V ref ). Conversely, the second terminal of the first capacitance (C 1 ) and the second terminal of the second capacitance (C 2 ) are connected to the input terminals of a differential operational amplifier (3440) of the differential integrator, whereby the charge difference between the capacitances (Ci, C 2 ) is transferred to the differential integrator. In this respect, a comparator with hysteresis (3446) triggers when the output signal of the differential integrator exceeds the hysteresis threshold of the comparator with hysteresis (3446).
In particular, two decoupling capacitances (C DEC1 , C DEC2 ) are connected between the input of the comparator with hysteresis (3446) and the output of the differential integrator, and the measurement systems uses two reset phases in order to store various disturbances to these decoupling capacitances (C DEC1 , C DEC2 ), thereby improving the precision of the measurement during the normal operating phase.

公开(公告)号：EP4254212A1

公开(公告)日：2023-10-04

申请号：EP23157086.2

申请日：2023-02-16

申请人： STMicroelectronics S.r.l.

发明人： CASTELLANO, Gerardo ,  GIORDANO, Antonio ,  RAIMONDI, Marcello

IPC分类号： G06F13/42 ,  B60R21/0132

摘要： A method to arm an airbag, the method including determining, by a system device (106), that an arming condition for the airbag has been met; delivering a communication to a master device (102) from the system device (106) to inform the master device (102) that the arming condition has been met; snooping the communication by an expansion device (106); and arming the airbag by the expansion device (106) in response to snooping the arming condition.

公开(公告)号：EP4187415A1

公开(公告)日：2023-05-31

申请号：EP22205161.7

申请日：2022-11-02

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

发明人： ZARGAR, Asif Rashid ,  GROSSIER, Nicolas Bernard ,  JAIN, Charul ,  COLOMBO, Roberto

IPC分类号： G06F21/44 ,  G06F21/55 ,  G06F21/76 ,  G06F21/79 ,  G06F21/85

摘要： A processing system (10a) is described. The processing system (10a) comprises a plurality of storage elements (113), wherein each storage element (113) is configured to receive a write request comprising a data bit (DATA) and store the received data bit (DATA) to a latch or flip-flop (1122). A hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation as a function of the logic level stored to the latch or flip-flop (1122) of a first storage element (113) of the plurality of storage elements (113). A non-volatile memory (104; 126) is configured to store data bits (CD, LCD) for the plurality of storage elements (113) and a hardware configuration circuit (108) is configured to read the data bits from the non-volatile memory (104; 126) and generate write requests in order to store the data bits to the storage elements (113).
Specifically, the hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation also as a function of the first tamper signal (TAMP). For this purpose, the first storage element (113) comprises a further latch or flip-flop (1124) and is configured to store, in response to the write request, the inverted version (1126) of the received data bit to the further latch or flip-flop (1124). The first storage element (113) comprises also a combinational logic circuit (1128) configured to compare the logic level stored to the latch or flip-flop (1122) of the first storage element (113) with the logic level stored to the further latch or flip-flop (1122) of the first storage element (113). The combinational logic circuit (1128) is configured to de-assert a first tamper signal (TAMP) associated with the first storage element (113) when the logic levels are different, and assert the first tamper signal (TAMP) when the logic levels are the same.

公开(公告)号：EP4152171A1

公开(公告)日：2023-03-22

申请号：EP22206499.0

申请日：2021-03-12

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

发明人： NANDLINGER, Rolf ,  OLEXA, Radek

IPC分类号： G06F13/40

摘要： A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (32 0 ..32 n ). Specifically, each interface circuit (32 0 ..32 n ) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).

公开(公告)号：EP3661056B1

公开(公告)日：2022-05-25

申请号：EP19209093.4

申请日：2019-11-14

发明人： COLOMBO,Roberto

IPC分类号： H03K5/19 ,  G06F11/30 ,  H03K19/007

公开(公告)号：EP3944457A1

公开(公告)日：2022-01-26

申请号：EP21185551.5

申请日：2021-07-14

申请人： STMicroelectronics Application GmbH

发明人： EKLER, Markus

IPC分类号： H02J7/00 ,  H01M10/48 ,  H03M7/30 ,  B60L58/10 ,  H01M10/42

摘要： A processing system (44a) configured to monitor the cell voltages of a given number (n) of cells of a rechargeable battery is described. The processing system (44a) comprises terminals (CP 0 ..CP n ) configured to be connected to the cells in order to receive the cell voltages, at least one analog to digital converter (448) is configured to generate digital samples of the cell voltages. The processing system (44a) comprises also a digital processing circuit (444a), a serial communication interface (440) and a transmission queue (452) used to interface the digital processing circuit (444a) with the serial communication interface (440), whereby the serial communication interface (440) and the digital processing circuit (444a) may operate in parallel. Specifically, the digital processing circuit (444a) is configured to synchronously acquire a given number (k) of digital samples (S 1,1 ..S n,k ) of each of the given number (n) of cell voltages and store the acquired digital samples (S 1,1 ..S n,k ) to a memory (DATA). Next, the digital processing circuit (444a) encodes the digital samples (S 1,1 ..S n,k ) stored to the memory (DATA) via a data compression module (450), thereby generating encoded data, and stores the encoded data to the transmission queue (452).
For example, the data compression module (450) may be configured to generate the encoded data by means of a dynamic range reduction operation (2004), wherein the data compression module (450) subtracts a given offset ( OFF ) from each digital sample (S 1,1 ..S n,k ), thereby generating values indicative of the dynamic variation of each sample with respect to the offset ( OFF ) , and removes a given number of most significant bits from each values. Preferably the given offset ( OFF ) is programmable.

公开(公告)号：EP3296923B1

公开(公告)日：2021-07-07

申请号：EP17162968.6

申请日：2017-03-27

发明人： GUARNERI, Ms. Nunziata Ivana ,  BRUNA, Mr. Arcangelo Ranieri ,  SPAMPINATO, Mr. Giuseppe

IPC分类号： G06K9/00 ,  G06T7/215

公开(公告)号：EP3570167B1

公开(公告)日：2020-11-11

申请号：EP19172340.2

申请日：2019-05-02

申请人： STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

发明人： CRITELLI, Mr. Rosalino ,  GUARNACCIA, Mr. Giuseppe ,  LE-GOASCOZ, Ms. Delphine ,  ANQUET, Mr. Nicolas

IPC分类号： G06F11/10