Invention Grant
- Patent Title: Partner-aware virtual microsectoring for sectored cache architectures
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Application No.: US14498963Application Date: 2014-09-26
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Publication No.: US10013352B2Publication Date: 2018-07-03
- Inventor: Sreenivas Subramoney , Jayesh Gaur , Mukesh Agrawal , Mainak Chaudhuri
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson DeVos Webster & Elliott LLP
- Main IPC: G06F12/12
- IPC: G06F12/12 ; G06F12/0811 ; G06F12/0813 ; G06F12/0842 ; G06F12/123
Abstract:
Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core.
Public/Granted literature
- US20160092369A1 Partner-Aware Virtual Microsectoring for Sectored Cache Architectures Public/Granted day:2016-03-31
Information query
