Invention Grant
- Patent Title: Copper etching integration scheme
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Application No.: US15463617Application Date: 2017-03-20
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Publication No.: US10020259B2Publication Date: 2018-07-10
- Inventor: Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/528 ; H01L21/768 ; H01L23/532 ; H01L23/522 ; H01L21/3213 ; H01L21/3105

Abstract:
The present disclosure relates to a method for forming an interconnect structure. In some embodiments, the method may be performed by forming an opening within a sacrificial layer. The sacrificial layer is over a substrate. A conductive material is formed within the opening and over the sacrificial layer. The conductive material within the opening defines a conductive body. The conductive material is patterned to define a conductive projection extending outward from the conductive body. The sacrificial layer is removed and a dielectric material is formed surrounding the conductive body and the conductive projection.
Public/Granted literature
- US20170194258A1 COPPER ETCHING INTEGRATION SCHEME Public/Granted day:2017-07-06
Information query
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