公开(公告)号：US11856866B2

公开(公告)日：2023-12-26

申请号：US17740145

申请日：2022-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H10N50/10 ,  G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01L23/5226 ,  H10B61/00 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A device includes a semiconductor substrate, a bottom conductive line, a bottom electrode, a magnetic tunneling junction (MTJ), and a residue. The bottom conductive line is over the semiconductor substrate. The bottom electrode is over the bottom conductive line. The MTJ is over the bottom electrode. The residue of the MTJ is on the sidewall of the bottom electrode and is spaced apart from the bottom conductive line.

公开(公告)号：US11569096B2

公开(公告)日：2023-01-31

申请号：US17327580

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

公开(公告)号：US10964888B2

公开(公告)日：2021-03-30

申请号：US16840100

申请日：2020-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pin-Ren Dai ,  Chung-Ju Lee ,  Chung-Te Lin ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Tai-Yen Peng ,  Chien-Min Lee ,  Wei-Hao Liao

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

公开(公告)号：US10354954B2

公开(公告)日：2019-07-16

申请号：US16017039

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L21/00 ,  H01L23/528 ,  H01L23/538 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/3213 ,  H01L23/522

Abstract: The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a metal projection protruding outward from an upper surface of the metal body. A dielectric layer is disposed over the substrate and surrounds the metal body and the metal projection. A barrier layer separates the metal body and the metal projection from the dielectric layer.

公开(公告)号：US10020259B2

公开(公告)日：2018-07-10

申请号：US15463617

申请日：2017-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L21/00 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/3105

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method for forming an interconnect structure. In some embodiments, the method may be performed by forming an opening within a sacrificial layer. The sacrificial layer is over a substrate. A conductive material is formed within the opening and over the sacrificial layer. The conductive material within the opening defines a conductive body. The conductive material is patterned to define a conductive projection extending outward from the conductive body. The sacrificial layer is removed and a dielectric material is formed surrounding the conductive body and the conductive projection.

公开(公告)号：US20140131872A1

公开(公告)日：2014-05-15

申请号：US13676260

申请日：2012-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a method of manufacturing an interconnect structure in which a sacrificial layer is formed over a semiconductor substrate followed by etching of the sacrificial layer to form a first feature. The metal layer is patterned and etched to form a second feature, followed by deposition of a low-k dielectric material. The method allows for formation of an interconnect structure without encountering the various problems presented by porous low-k dielectric damage.

Abstract translation: 本公开涉及一种制造互连结构的方法，其中牺牲层形成在半导体衬底上，随后蚀刻牺牲层以形成第一特征。 金属层被图案化和蚀刻以形成第二特征，随后沉积低k电介质材料。 该方法允许形成互连结构，而不会遇到由多孔低k电介质损伤所呈现的各种问题。

公开(公告)号：US12302761B2

公开(公告)日：2025-05-13

申请号：US18474173

申请日：2023-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H10N50/10 ,  G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A device includes a first dielectric layer, a magnetic tunnel junction (MTJ), an oxide layer, a cap layer, and a second dielectric layer. The MTJ is over the first dielectric layer. The oxide layer is over the first dielectric layer. The cap layer is over the first dielectric layer. The cap layer is in contact with a sidewall of the MTJ and a sidewall of the oxide layer. The second dielectric layer is over the cap layer.

公开(公告)号：US11849645B2

公开(公告)日：2023-12-19

申请号：US17833688

申请日：2022-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/10 ,  H10N50/01 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: An integrated circuit includes a substrate, a bottom electrode, a dielectric layer, a metal-containing compound layer, a resistance switching element, and a top electrode. The bottom electrode is over the substrate, the bottom electrode having a bottom portion and a top portion over the bottom portion. The bottom portion of the bottom electrode has a sidewall slanted with respect to a sidewall of the top portion of the bottom electrode. The dielectric layer surrounds the bottom portion of the bottom electrode. The metal-containing compound layer surrounds the top portion of the bottom electrode. A top end of the sidewall of the bottom portion of the bottom electrode is higher than a bottom surface of the metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.

公开(公告)号：US11355701B2

公开(公告)日：2022-06-07

申请号：US17001282

申请日：2020-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: An integrated circuit includes a substrate, a dielectric layer, an etch stop layer, a bottom electrode, a resistance switching element, and a top electrode. The dielectric layer is over the substrate. The etch stop layer is over the dielectric layer, in which the dielectric layer has a first portion directly under the etch stop layer. The bottom electrode penetrates through the etch stop layer and the dielectric layer, in which the dielectric layer has a second portion directly under the bottom electrode, and a top of the first portion of the dielectric layer is lower than a top of the second portion of the dielectric layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.

公开(公告)号：US11171052B2

公开(公告)日：2021-11-09

申请号：US16396965

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311

Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a conductive line layer over a semiconductor substrate. The conductive line layer includes a metal line. The method also includes forming a conductive pillar on and in contact with the metal line. The method further includes depositing a dielectric layer over the conductive line layer to cover the conductive pillar, and etching the dielectric layer to form a trench. The conductive pillar is exposed through the trench. In addition, the method includes filling the trench with a conductive material to form a conductive line.