- Patent Title: Dynamically controlling cache size to maximize energy efficiency
-
Application No.: US15270208Application Date: 2016-09-20
-
Publication No.: US10067553B2Publication Date: 2018-09-04
- Inventor: Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F1/32 ; G06F12/084 ; G06F12/0864 ; G06F1/28 ; G06F12/0802 ; G06F12/0846
Abstract:
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
Public/Granted literature
- US20170010656A1 Dynamically Controlling Cache Size To Maximize Energy Efficiency Public/Granted day:2017-01-12
Information query
