公开(公告)号：US20220283619A1

公开(公告)日：2022-09-08

申请号：US17824984

申请日：2022-05-26

申请人： Intel Corporation

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC分类号： G06F1/324 ,  G06F1/3296

摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US11435816B2

公开(公告)日：2022-09-06

申请号：US17215104

申请日：2021-03-29

申请人： Intel Corporation

发明人： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

IPC分类号： G06F1/00 ,  G06F1/3296 ,  G06F1/3228 ,  G06F9/30 ,  G06F1/324

摘要： In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

公开(公告)号：US10564699B2

公开(公告)日：2020-02-18

申请号：US16223818

申请日：2018-12-18

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC分类号： G06F12/00 ,  G06F1/3234 ,  G06F12/0864 ,  G06F12/084 ,  G06F1/28 ,  G06F12/0802 ,  G06F1/3287 ,  G06F12/0846

摘要： In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US10394300B2

公开(公告)日：2019-08-27

申请号：US15966397

申请日：2018-04-30

申请人： Intel Corporation

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/26

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US10216246B2

公开(公告)日：2019-02-26

申请号：US15281651

申请日：2016-09-30

申请人： Intel Corporation

发明人： Doron Rajwan ,  Efraim Rotem ,  Eliezer Weissmann ,  Avinash N. Ananthakrishnan ,  Dorit Shapira

IPC分类号： G06F1/32 ,  G06F9/50 ,  G06F1/3228 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3237 ,  G06F17/50 ,  G06F1/3234 ,  G06F1/3293

摘要： In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US09760160B2

公开(公告)日：2017-09-12

申请号：US14722518

申请日：2015-05-27

申请人： Intel Corporation

发明人： Eliezer Weissmann ,  Efraim Rotem ,  Hisham Abu Salah ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Gal Leibovich ,  Yevgeni Sabin ,  Shay Levy

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F9/50

CPC分类号： G06F1/3287 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

摘要： In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

公开(公告)号：US20170090945A1

公开(公告)日：2017-03-30

申请号：US14866584

申请日：2015-09-25

申请人： Intel Corporation

发明人： Doron Rajwan ,  Eliezer Weissmann ,  Yoni Aizik ,  Itai Feit ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC分类号： G06F9/44 ,  G06F1/24

CPC分类号： G06F11/3024 ,  G01V11/002 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3452 ,  G06F11/348 ,  G06F2201/88

摘要： Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.

公开(公告)号：US09292068B2

公开(公告)日：2016-03-22

申请号：US13782539

申请日：2013-03-01

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells ,  Nadav Shulman

IPC分类号： G06F13/00 ,  G06F1/32 ,  G06F1/26 ,  G06F9/38

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

摘要： In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

公开(公告)号：US20160026229A1

公开(公告)日：2016-01-28

申请号：US14875930

申请日：2015-10-06

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Jeremy J. Shrall ,  Eric C. Samson ,  Eliezer Weissmann ,  Ryan Wells

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/26 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3243 ,  G06F13/14 ,  Y02D10/126

摘要： In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

公开(公告)号：US11740682B2

公开(公告)日：2023-08-29

申请号：US17824984

申请日：2022-05-26

申请人： Intel Corporation

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC分类号： G06F1/00 ,  G06F1/324 ,  G06F1/3296

CPC分类号： G06F1/324 ,  G06F1/3296

摘要： A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.