The output circuit includes: a control voltage generating circuit configured to generate a control voltage; a first MOS transistor having a gate for receiving the control voltage; a second MOS transistor having a gate to which a first input signal is input; a third MOS transistor having a gate to which a second input signal is input; and a fourth MOS transistor which has a gate connected to a source of the first MOS transistor, and a drain connected to an output terminal, and is configured to be driven with the first input signal and the second input signal to output an output signal to the output terminal. The control voltage generating circuit is configured to absorb fluctuations in control voltage, which are caused due to changes in first input signal and second input signal, to thereby maintain the control voltage at a predetermined voltage.