Invention Grant
- Patent Title: Circuit architectures for protecting against PoDL wire faults
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Application No.: US14956308Application Date: 2015-12-01
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Publication No.: US10090666B2Publication Date: 2018-10-02
- Inventor: Andrew J. Gardner , Jeffrey L. Heath , David Dwelley
- Applicant: Linear Technology Corporation
- Applicant Address: US CA Milpitas
- Assignee: Linear Technology Corporation
- Current Assignee: Linear Technology Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Patent Law Group LLP
- Agent Brian D. Ogonowsky
- Main IPC: H02H3/20
- IPC: H02H3/20 ; H02H3/087 ; H02H3/06 ; H02H11/00

Abstract:
In one embodiment, a PoDL system includes a PSE that uses high side and low side circuit breakers that uncouple the PSE voltage source from the wire pair in the event that a fault is detected. Faults may include a temporary short to ground, or to a battery voltage, or between the wires. The breakers perform an automatic retry operation in the event the fault has been removed. The voltages on the wires in the wire pair may be monitored to determine whether the voltages are within a normal range or indicative of a fault condition. Other embodiments are disclosed.
Public/Granted literature
- US20160156173A1 CIRCUIT ARCHITECTURES FOR PROTECTING AGAINST PoDL WIRE FAULTS Public/Granted day:2016-06-02
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