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公开(公告)号：US20170310491A1
公开(公告)日：2017-10-26
申请号：US15479187
申请日：2017-04-04
Applicant: Linear Technology Corporation
Inventor： David M. Dwelley , Andrew J. Gardner
IPC: H04L12/10
CPC classification number: H04L12/10 , G06F1/266 , H04B3/44 , H04L12/40045 , H04L12/403 , H04L12/437 , H04L12/44
Abstract: In one embodiment, a master device has a first port and a second port and initially applies a DC voltage only to the first port. A plurality of slave devices, each have a third port and a fourth port, are serially connected to the master device in a ring, via conductors, starting at the first port and ending at the second port. The conductors simultaneously carry the DC voltage and differential data. Each slave device, after performing a detection routine, then sequentially applies the DC voltage to the adjacent downstream slave device in a first direction around the ring. If the master does not detect the presence of the DC voltage at its second port, the master device applies the DC voltage to both the first port and the second port to sequentially power up the slave devices in both directions around the ring of slave devices.
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公开(公告)号：US20160337138A1
公开(公告)日：2016-11-17
申请号：US15134117
申请日：2016-04-20
Applicant: Linear Technology Corporation
Inventor： Andrew J. Gardner , David M. Dwelley , Heath Stewart
IPC: H04L12/10
CPC classification number: H04L12/10 , H04L12/12 , H04L12/403 , Y02D50/40
Abstract: A system includes a master and a slave coupled via a wire pair for transmitting differential data. The master and slave are each powered by a local DC power supply. In a normal mode, a DC voltage and differential data are supplied over the same wire pair. The differential data is processed by a PHY AC-coupled to the wire pair. To enter a low power sleep mode, such as due to a temporary non-use of the system, the master interrupts the DC voltage on the wire pair, which signals to the slave to enter the sleep mode. The system is woken up by reapplying the DC voltage to the wire pair to signal to the slave to wake up. Only the DC path, and not the data path, is used for signaling the sleep mode and awake mode, so the data path can be disabled to conserve power.
Abstract translation: 系统包括通过线对耦合的主机和从机，用于发送差分数据。 主机和从机都由本地直流电源供电。 在正常模式下，通过相同的线对提供直流电压和差分数据。 差分数据由耦合到线对的PHY处理。 要进入低功耗睡眠模式，例如由于暂时不使用系统，主机会中断线对上的直流电压，从而将信号通知从机进入睡眠模式。 通过将直流电压重新应用到线对来唤醒系统，以向从机发信号进行唤醒。 只有DC路径，而不是数据路径用于信令睡眠模式和唤醒模式，因此可以禁用数据路径以节省功耗。
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3.发明申请公开(公告)号：US20160054777A1
公开(公告)日：2016-02-25
申请号：US14831632
申请日：2015-08-20
Applicant: Linear Technology Corporation
Inventor： David Dwelley , Andrew J. Gardner
CPC classification number: G06F1/3206 , G06F1/263 , G06F1/3287 , G06F1/3296 , G06F13/4022 , G06F13/4282 , H04L12/10 , H04L12/40045
Abstract: A PoDL system includes a PSE supplying DC power and Ethernet data over a single twisted wire pair to a PD. Prior to coupling the DC voltage source to the wire pair, the PD needs to receive sufficient power to perform a detection and classification routine with the PSE to determine whether the PD is PoDL-compatible. The PSE has a low current, pull-up current source coupled to a first wire in the wire pair via a first inductor. This pull-up current charges a capacitor in the PD to a desired operating voltage, and the operating voltage is used to power a PD logic circuit. The PD logic circuit and a PSE logic circuit then control pull-down transistors to communicate detection and classification data via the first wire. After the handshaking phase, the PSE then applies the DC voltage source across the wire pair to power the PD for normal operation.
Abstract translation: PoDL系统包括通过单个双绞线对PD提供直流电源和以太网数据的PSE。 在将直流电压源耦合到线对之前，PD需要接收足够的电力以执行与PSE的检测和分类例程，以确定PD是否与PoDL兼容。 PSE具有通过第一电感器耦合到线对中的第一线的低电流，上拉电流源。 该上拉电流将PD中的电容器充电到期望的工作电压，并且使用工作电压为PD逻辑电路供电。 然后，PD逻辑电路和PSE逻辑电路控制下拉晶体管，以经由第一线路传送检测和分类数据。 在握手阶段之后，PSE将通过电线对施加直流电压源，为PD供电以进行正常工作。
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公开(公告)号：US20150333935A1
公开(公告)日：2015-11-19
申请号：US14712855
申请日：2015-05-14
Applicant: Linear Technology Corporation
Inventor： Andrew J. Gardner , David Dwelley , Jeffrey L. Heath
CPC classification number: H04L25/0266 , H02M3/156 , H02M3/158 , H02M2001/0029 , H04L12/10 , H04L25/0272
Abstract: A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and differential Ethernet data over a single twisted wire pair to a Powered Device (PD). Due to start-up perturbations, PD load current variations, and other causes, dV/dt noise is introduced in the power signal. Such noise may be misinterpreted as data unless mitigated somehow. Rather than increasing the values of the passive filtering components conventionally used for decoupling/coupling the power and data from/to the wire pair, active circuitry is provided in the PSE, PD, or both to limit dV/dt in the power signal. Such circuitry may be implemented on the same chip as the PSE controller or PD controller. Therefore, the sizes of the passive components in the decoupling/coupling networks may be reduced.
Abstract translation: 数据线电源（PoDL）系统包括通过单个双绞线对有源设备（PD）提供直流电源和差分以太网数据的电源设备（PSE）。 由于启动扰动，PD负载电流变化和其他原因，dV / dt噪声被引入功率信号。 这种噪声可能被误解为数据，除非以某种方式得到缓解。 不是增加常规用于从/对线对去耦/耦合功率和数据的无源滤波组件的值，而是在PSE，PD或两者中提供有源电路以限制功率信号中的dV / dt。 这种电路可以在与PSE控制器或PD控制器相同的芯片上实现。 因此，可以减小去耦/耦合网络中的无源组件的尺寸。
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公开(公告)号：US10547206B2
公开(公告)日：2020-01-28
申请号：US15723631
申请日：2017-10-03
Applicant: Linear Technology Corporation
Inventor： Heath Stewart , Andrew J. Gardner , David Stover , David Dwelley , Jeffrey L. Heath
Abstract: One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.
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Patent Agency Ranking
公开(公告)号：US10444823B2
公开(公告)日：2019-10-15
申请号：US15653058
申请日：2017-07-18
Applicant: Linear Technology Corporation
Inventor： Andrew J. Gardner
IPC: G06F1/3296 , H04L25/02 , H04L12/10 , H04B3/54 , H04B3/56 , G06F1/3287 , H04L12/40
Abstract: In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuity to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.
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公开(公告)号：US20180024620A1
公开(公告)日：2018-01-25
申请号：US15653058
申请日：2017-07-18
Applicant: Linear Technology Corporation
Inventor： Andrew J. Gardner
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/3287 , H04B3/548 , H04B3/56 , H04B2203/547 , H04B2203/5483 , H04L12/10 , H04L12/40045 , H04L25/0266 , H04L25/0276 , H04L25/0282 , H04L25/0298
Abstract: In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuity to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.
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公开(公告)号：US09860072B2
公开(公告)日：2018-01-02
申请号：US15134117
申请日：2016-04-20
Applicant: Linear Technology Corporation
Inventor： Andrew J. Gardner , David M. Dwelley , Heath Stewart
CPC classification number: H04L12/10 , H04L12/12 , H04L12/403 , Y02D50/40
Abstract: A system includes a master and a slave coupled via a wire pair for transmitting differential data. The master and slave are each powered by a local DC power supply. In a normal mode, a DC voltage and differential data are supplied over the same wire pair. The differential data is processed by a PHY AC-coupled to the wire pair. To enter a low power sleep mode, such as due to a temporary non-use of the system, the master interrupts the DC voltage on the wire pair, which signals to the slave to enter the sleep mode. The system is woken up by reapplying the DC voltage to the wire pair to signal to the slave to wake up. Only the DC path, and not the data path, is used for signaling the sleep mode and awake mode, so the data path can be disabled to conserve power.
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公开(公告)号：US09967104B2
公开(公告)日：2018-05-08
申请号：US14945260
申请日：2015-11-18
Applicant: Linear Technology Corporation
Inventor： Andrew J. Gardner , Jeffrey L. Heath
CPC classification number: H04L12/10 , B60L3/0069 , G01R31/024 , H02H3/16 , H04L12/40045 , H04L25/08 , H04L41/0681 , H04L43/0811 , Y04S40/166 , Y04S40/168
Abstract: Circuits and techniques are described for detecting a ground fault leak between the PSE and the PD. Prior to PoDL voltage being applied to the PD, a test switch is temporarily closed for sensing a voltage drop in a loop between the positive terminal of the PSE voltage source and any ground leakage path between the PSE and the PD. If the resistance of the ground leakage path is below a certain threshold, a fault is declared. A similar test may be performed without a test switch by supplying a known test current through the loop and sensing the voltage drop. Another test is to connect the positive terminal of the PSE voltage source to the loop and sense the resulting current. After the full PoDL voltage is applied to the PD, a ground fault may be detected by sensing the equivalence between the source and return PSE currents.
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公开(公告)号：US20180115191A1
公开(公告)日：2018-04-26
申请号：US15723631
申请日：2017-10-03
Applicant: Linear Technology Corporation
Inventor： Heath Stewart , Andrew J. Gardner , David Stover , David Dwelley , Jeffrey L. Heath
Abstract: One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.
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