中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.015 seconds)

    PoDL SYSTEM WITH ACTIVE dV/dt and dI/dt CONTROL
    1.
    发明申请
    PoDL SYSTEM WITH ACTIVE dV/dt and dI/dt CONTROL 有权
    具有活动dV / dt和dI / dt控制的PoDL系统

    公开(公告)号：US20150333935A1

    公开(公告)日：2015-11-19

    申请号：US14712855

    申请日：2015-05-14

    Applicant: Linear Technology Corporation

    Inventor： Andrew J. Gardner ,  David Dwelley ,  Jeffrey L. Heath

    IPC: H04L25/02 ,  H04L12/10 ,  H02M3/158

    CPC classification number: H04L25/0266 ,  H02M3/156 ,  H02M3/158 ,  H02M2001/0029 ,  H04L12/10 ,  H04L25/0272

    Abstract: A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and differential Ethernet data over a single twisted wire pair to a Powered Device (PD). Due to start-up perturbations, PD load current variations, and other causes, dV/dt noise is introduced in the power signal. Such noise may be misinterpreted as data unless mitigated somehow. Rather than increasing the values of the passive filtering components conventionally used for decoupling/coupling the power and data from/to the wire pair, active circuitry is provided in the PSE, PD, or both to limit dV/dt in the power signal. Such circuitry may be implemented on the same chip as the PSE controller or PD controller. Therefore, the sizes of the passive components in the decoupling/coupling networks may be reduced.

    Abstract translation: 数据线电源（PoDL）系统包括通过单个双绞线对有源设备（PD）提供直流电源和差分以太网数据的电源设备（PSE）。 由于启动扰动，PD负载电流变化和其他原因，dV / dt噪声被引入功率信号。 这种噪声可能被误解为数据，除非以某种方式得到缓解。 不是增加常规用于从/对线对去耦/耦合功率和数据的无源滤波组件的值，而是在PSE，PD或两者中提供有源电路以限制功率信号中的dV / dt。 这种电路可以在与PSE控制器或PD控制器相同的芯片上实现。 因此，可以减小去耦/耦合网络中的无源组件的尺寸。

    Fault-tolerant power network
    4.
    发明授权
    Fault-tolerant power network 有权

    公开(公告)号：US10547206B2

    公开(公告)日：2020-01-28

    申请号：US15723631

    申请日：2017-10-03

    Applicant: Linear Technology Corporation

    Inventor： Heath Stewart ,  Andrew J. Gardner ,  David Stover ,  David Dwelley ,  Jeffrey L. Heath

    IPC: H02J13/00 ,  H04L12/10 ,  H04L12/24 ,  H04L12/26 ,  H04L12/437 ,  G05B15/02 ,  G01R27/16

    Abstract: One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.

    Maintain power signature controller at power interface of PoE or PoDL system
    5.
    发明授权
    Maintain power signature controller at power interface of PoE or PoDL system 有权

    公开(公告)号：US10263794B2

    公开(公告)日：2019-04-16

    申请号：US15582445

    申请日：2017-04-28

    Applicant: Linear Technology Corporation

    Inventor： Michael Paul ,  David M. Stover ,  Heath D. Stewart ,  Jeffrey L. Heath

    IPC: H04L12/10 ,  G06F1/26 ,  H04L12/40

    Abstract: The invention pertains to systems where DC power is supplied by a PSE to a PD, such as over differential data wire pairs. IEEE standards require a minimum current to be drawn from the PD in order for the PSE to continue supplying the DC voltage. If the PD is in a low power mode, the PSE will normally discontinue supplying the DC voltage, which then requires a new detection and classification routine for powering up again. To avoid this, a “maintain power signature” controller provides a periodic current pulse by a current source connected between the PD input and the PD's full bridge rectifier. Any droop in the DC voltage that reverse biases the full bridge rectifier while the PD is in its low power mode will not affect the current pulse, so the PSE continues to supply the DC voltage.

    MAINTAIN POWER SIGNATURE CONTROLLER AT POWER INTERFACE OF PoE OR PoDL SYSTEM
    6.
    发明申请
    MAINTAIN POWER SIGNATURE CONTROLLER AT POWER INTERFACE OF PoE OR PoDL SYSTEM 审中-公开

    公开(公告)号：US20170338969A1

    公开(公告)日：2017-11-23

    申请号：US15582445

    申请日：2017-04-28

    Applicant: Linear Technology Corporation

    Inventor： Michael Paul ,  David M. Stover ,  Heath D. Stewart ,  Jeffrey L. Heath

    IPC: H04L12/10

    CPC classification number: H04L12/10 ,  G06F1/26 ,  H04L12/40045

    Abstract: The invention pertains to systems where DC power is supplied by a PSE to a PD, such as over differential data wire pairs. IEEE standards require a minimum current to be drawn from the PD in order for the PSE to continue supplying the DC voltage. If the PD is in a low power mode, the PSE will normally discontinue supplying the DC voltage, which then requires a new detection and classification routine for powering up again. To avoid this, a “maintain power signature” controller provides a periodic current pulse by a current source connected between the PD input and the PD's full bridge rectifier. Any droop in the DC voltage that reverse biases the full bridge rectifier while the PD is in its low power mode will not affect the current pulse, so the PSE continues to supply the DC voltage.

    FAULT-TOLERANT POWER NETWORK
    8.
    发明申请
    FAULT-TOLERANT POWER NETWORK 审中-公开

    公开(公告)号：US20180115191A1

    公开(公告)日：2018-04-26

    申请号：US15723631

    申请日：2017-10-03

    Applicant: Linear Technology Corporation

    Inventor： Heath Stewart ,  Andrew J. Gardner ,  David Stover ,  David Dwelley ,  Jeffrey L. Heath

    IPC: H02J13/00 ,  G05B15/02

    Abstract: One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.

    CIRCUIT ARCHITECTURES FOR PROTECTING AGAINST PoDL WIRE FAULTS
    9.
    发明申请
    CIRCUIT ARCHITECTURES FOR PROTECTING AGAINST PoDL WIRE FAULTS 审中-公开
    用于保护PoDL线路故障的电路架构

    公开(公告)号：US20160156173A1

    公开(公告)日：2016-06-02

    申请号：US14956308

    申请日：2015-12-01

    Applicant: Linear Technology Corporation

    Inventor： Andrew J. Gardner ,  Jeffrey L. Heath ,  David Dwelley

    IPC: H02H3/20 ,  H02H3/087

    CPC classification number: H02H3/202 ,  H02H3/06 ,  H02H3/207 ,  H02H11/002

    Abstract: In one embodiment, a PoDL system includes a PSE that uses high side and low side circuit breakers that uncouple the PSE voltage source from the wire pair in the event that a fault is detected. Faults may include a temporary short to ground, or to a battery voltage, or between the wires. The breakers perform an automatic retry operation in the event the fault has been removed. The voltages on the wires in the wire pair may be monitored to determine whether the voltages are within a normal range or indicative of a fault condition. Other embodiments are disclosed.

    Abstract translation: 在一个实施例中，PoDL系统包括使用高侧和低侧断路器的PSE，其在检测到故障的情况下将PSE电压源与电线对分离。 故障可能包括临时短路接地或电池电压，或电线之间。 断路器在故障消除的情况下执行自动重试操作。 可以监测线对中的导线上的电压，以确定电压是在正常范围内还是指示故障状态。 公开了其他实施例。

    DETECTING GROUND ISOLATION FAULT IN ETHERNET PoDL SYSTEM
    10.
    发明申请
    DETECTING GROUND ISOLATION FAULT IN ETHERNET PoDL SYSTEM 有权
    检测以太网PoDL系统中的地面隔离故障

    公开(公告)号：US20160142217A1

    公开(公告)日：2016-05-19

    申请号：US14945260

    申请日：2015-11-18

    Applicant: Linear Technology Corporation

    Inventor： Andrew J. Gardner ,  Jeffrey L. Heath

    IPC: H04L12/10

    CPC classification number: H04L12/10 ,  B60L3/0069 ,  G01R31/024 ,  H02H3/16 ,  H04L12/40045 ,  H04L25/08 ,  H04L41/0681 ,  H04L43/0811 ,  Y04S40/166 ,  Y04S40/168

    Abstract: Circuits and techniques are described for detecting a ground fault leak between the PSE and the PD. Prior to PoDL voltage being applied to the PD, a test switch is temporarily closed for sensing a voltage drop in a loop between the positive terminal of the PSE voltage source and any ground leakage path between the PSE and the PD. If the resistance of the ground leakage path is below a certain threshold, a fault is declared. A similar test may be performed without a test switch by supplying a known test current through the loop and sensing the voltage drop. Another test is to connect the positive terminal of the PSE voltage source to the loop and sense the resulting current. After the full PoDL voltage is applied to the PD, a ground fault may be detected by sensing the equivalence between the source and return PSE currents.

    Abstract translation: 描述了用于检测PSE和PD之间的接地故障泄漏的电路和技术。 在PoDL电压施加到PD之前，测试开关暂时闭合，用于感测PSE电压源的正极端子与PSE和PD之间的任何接地泄漏路径之间的环路中的电压降。 如果地面泄漏路径的电阻低于一定阈值，则会声明故障。 可以通过提供已知的测试电流通过环路并感测电压降而不用测试开关进行类似的测试。 另一个测试是将PSE电压源的正极连接到环路并感测所得到的电流。 在将完整的PoDL电压施加到PD之后，可以通过感测源极和返回PSE电流之间的等效性来检测接地故障。

Patent Agency Ranking