In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.