-
公开(公告)号：US12216515B2
公开(公告)日：2025-02-04
申请号：US18497443
申请日：2023-10-30
Applicant: Apple Inc.
Inventor： Shawn Searles , Fabio Gozzini , Sanjay Pant , Inder M. Sodhi
Abstract: A power converter circuit included in a computer system may include a phase circuit and a sample circuit. The phase circuit compares a voltage level of the regulated power supply node to a reference voltage to generate a demand current that is used to adjust the voltage level of the regulated power supply node. The phase circuit also digitizes the demand current and stores the resultant bit stream in a memory circuit. The sample circuit generates timestamp information that points to particular storage locations in the memory circuit that correspond to trigger events, allowing the operation of the power converter circuit to be analyzed during different circumstances as well as to adjust operating parameters of the power converter circuit.
-
公开(公告)号：US11960341B2
公开(公告)日：2024-04-16
申请号：US17676665
申请日：2022-02-21
Applicant: Apple Inc.
Inventor： Jamie L. Langlinais , Inder M. Sodhi , Lior Zimet , Keith Cox
IPC: G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3293 , G06F1/3296
CPC classification number: G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3293 , G06F1/3296
Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.
-
公开(公告)号：US20230060391A1
公开(公告)日：2023-03-02
申请号：US17412230
申请日：2021-08-25
Applicant: Apple Inc.
Inventor： Keith Cox , Jamie L. Langlinais , Inder M. Sodhi
Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level suppl voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.
-
公开(公告)号：US11169585B2
公开(公告)日：2021-11-09
申请号：US16543334
申请日：2019-08-16
Applicant: Apple Inc.
Inventor： Achmed R. Zahir , Inder M. Sodhi , John H. Kelm
Abstract: Systems, methods and mechanisms for efficiently reporting sensor data of multiple processing units. In various embodiments, a computing system includes processing units and a power management unit. The processing units include multiple sensors for measuring a variety of types of sensor data. If the sensor values exceed corresponding thresholds, then a processing unit sends the sensor values to the power management unit. Logic in the power management unit stores received sensor values. When the logic determines behavior of a processing unit changes, the logic updates one or more sensor thresholds for the processing unit for changing a frequency of reporting one or more sensor values of the processing unit. The logic sends the updated one or more sensor thresholds to the processing unit. The logic updates more operating modes and operating states for the processing units based on the received sensor values.
-
公开(公告)号：US20240427391A1
公开(公告)日：2024-12-26
申请号：US18438782
申请日：2024-02-12
Applicant: Apple Inc.
Inventor： Inder M. Sodhi , Achmed R. Zahir , Carmel Yamberger , Daniele Perretta , Jan Krellner , Ron Neuman , James S. Ismail , Keith Cox
Abstract: Techniques are disclosed relating to electromigration control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor operating conditions, implement control for one or more electromigration loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid electromigration issues, potentially with reduced impact on processor performance relative to traditional techniques.
-
Patent Agency Ranking
公开(公告)号：US12135602B2
公开(公告)日：2024-11-05
申请号：US17573268
申请日：2022-01-11
Applicant: Apple Inc.
Inventor： Doron Rajwan , Inder M. Sodhi , Keith Cox , Jung Wook Cho , Kevin I. Park , Tal Kuzi
IPC: G06F1/3296 , G06F1/3234 , G06F1/324
Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.
-
公开(公告)号：US20230384846A1
公开(公告)日：2023-11-30
申请号：US18326430
申请日：2023-05-31
Applicant: Apple Inc.
Inventor： Keith Cox , Jamie L. Langlinais , Inder M. Sodhi
Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supp1 voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.
-
公开(公告)号：US11698669B2
公开(公告)日：2023-07-11
申请号：US17412230
申请日：2021-08-25
Applicant: Apple Inc.
Inventor： Keith Cox , Jamie L. Langlinais , Inder M. Sodhi
CPC classification number: G06F1/26 , H02M3/155 , G06F1/263 , H02M1/007 , H02M1/0067
Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supply voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.
-
公开(公告)号：US20230101217A1
公开(公告)日：2023-03-30
申请号：US17573268
申请日：2022-01-11
Applicant: Apple Inc.
Inventor： Doron Rajwan , Inder M. Sodhi , Keith Cox , Jung Wook Cho , Kevin I. Park , Tal Kuzi
IPC: G06F1/3296 , G06F1/324 , G06F1/3234
Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.
-
公开(公告)号：US20230069344A1
公开(公告)日：2023-03-02
申请号：US17676665
申请日：2022-02-21
Applicant: Apple Inc.
Inventor： Jamie L. Langlinais , Inder M. Sodhi , Lior Zimet , Keith Cox
IPC: G06F1/3296 , G06F1/3206
Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.
-
-
-
-
-
-
-
-
-
Search Results
46
records
(took 0.024 seconds)
