公开(公告)号：US20220327977A1

公开(公告)日：2022-10-13

申请号：US17680103

申请日：2022-02-24

Applicant: Apple Inc.

Inventor： Kevin W. Sliech ,  Jason N. Gomez ,  David A. Hartley ,  Chengrui Le ,  Paolo Sacchetto ,  Arthur L. Spence

IPC: G09G3/20

Abstract: In an embodiment, an electronic device includes an electronic display. The electronic display provides a programmable latency period in response to receiving a first image frame corresponding to first image frame data. The electronic display also displays the first image frame after the programmable latency period and during display of the first image frame, receives a second image frame corresponding to second image frame data. The electronic display also repeats display of the first image frame in response to receiving the second image frame.

公开(公告)号：US11615727B2

公开(公告)日：2023-03-28

申请号：US17680103

申请日：2022-02-24

Applicant: Apple Inc.

Inventor： Kevin W. Sliech ,  Jason N. Gomez ,  David A. Hartley ,  Chengrui Le ,  Paolo Sacchetto ,  Arthur L. Spence

IPC: G09G3/20

Abstract: In an embodiment, an electronic device includes an electronic display. The electronic display provides a programmable latency period in response to receiving a first image frame corresponding to first image frame data. The electronic display also displays the first image frame after the programmable latency period and during display of the first image frame, receives a second image frame corresponding to second image frame data. The electronic display also repeats display of the first image frame in response to receiving the second image frame.

公开(公告)号：US20170220100A1

公开(公告)日：2017-08-03

申请号：US15168472

申请日：2016-05-31

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  David A. Hartley ,  Inder M. Sodhi

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3237 ,  G06F1/324 ,  G06F9/3869 ,  Y02D10/128 ,  Y02D10/172

Abstract: In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

公开(公告)号：US10209767B2

公开(公告)日：2019-02-19

申请号：US15168472

申请日：2016-05-31

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  David A. Hartley ,  Inder M. Sodhi

IPC: G06F1/32 ,  G06F9/32 ,  G06F9/38

Abstract: In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

公开(公告)号：US09495926B2

公开(公告)日：2016-11-15

申请号：US14557001

申请日：2014-12-01

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Peter F. Holland ,  Arthur L. Spence ,  Axel B. Schumacher ,  David A. Hartley

IPC: G06F3/038 ,  G09G3/36 ,  G06T1/20 ,  G06T1/60

CPC classification number: G09G3/3614 ,  G06T1/20 ,  G06T1/60 ,  G09G3/3696 ,  G09G2320/0266 ,  G09G2330/021 ,  G09G2340/0435

Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.

Abstract translation: 用于防止显示器的显示面板上的电荷累积的系统，装置和方法。 显示管道被配置为使用可变帧刷新率驱动显示器。 显示器也可以由极性反转节奏驱动，以在背对背框上交替显示面板上的极性。 在某些情况下，如果在包含用于处理相应帧的配置数据的帧分组中指定的帧刷新率节奏可以在切换到第一帧刷新率之前以奇数帧显示在显示面板上的电荷累积 第二帧刷新率。 因此，在这些情况下，显示管线可以覆盖给定帧的帧刷新率设置，以使得以第一帧刷新率显示偶数帧。