A receiving circuit includes a deserializer circuit configured to convert serial data to parallel data in accordance with an operating clock, a phase difference detection circuit configured to detect a phase difference between the operating clock and the serial data on the basis of the parallel data, a control circuit configured to determine a phase adjustment amount for shifting a phase of the operating clock by 1 bit of the serial data in accordance with a result of integration of the phase difference when a separation of the parallel data output from the deserializer circuit is not logically correct, and a phase interpolator circuit configured to cause the phase of the operating clock to shift by the 1 bit of the serial data by using the phase adjustment amount in accordance with the result of the integration of the phase difference.