Device structures and fabrication methods for a vertical field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A first spacer layer is formed on the first source/drain region. A dielectric layer is formed that extends in the vertical direction from the first spacer layer to a top surface of the semiconductor fin. The dielectric layer is recessed in the vertical direction, and a second spacer layer is formed on the recessed dielectric layer such that the dielectric layer is located in the vertical direction between the first spacer layer and the second spacer layer. After the dielectric layer is removed to open a space between the first spacer layer and the second spacer layer, a gate electrode is formed in the space. The vertical field-effect transistor has a gate length that is equal to a thickness of the recessed dielectric layer.