公开(公告)号：US10529858B2

公开(公告)日：2020-01-07

申请号：US15913194

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

公开(公告)号：US20190181012A1

公开(公告)日：2019-06-13

申请号：US16265784

申请日：2019-02-01

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/24 ,  H01L21/768 ,  H01L29/08 ,  H01L29/78 ,  H01L29/267

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US10276573B2

公开(公告)日：2019-04-30

申请号：US15168382

申请日：2016-05-31

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/06 ,  H01L21/308 ,  H01L21/033 ,  H01L29/78 ,  H01L29/165 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

公开(公告)号：US10008582B2

公开(公告)日：2018-06-26

申请号：US15361790

申请日：2016-11-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.

公开(公告)号：US09887196B2

公开(公告)日：2018-02-06

申请号：US14583842

申请日：2014-12-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L27/092 ,  H01L29/10 ,  H01L27/12 ,  H01L21/84 ,  H01L29/165 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/06 ,  H01L21/033 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/7849

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

公开(公告)号：US09685555B2

公开(公告)日：2017-06-20

申请号：US14584161

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Nicolas Loubet ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L29/7856 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/0657 ,  H01L29/4975 ,  H01L29/6681 ,  H01L2029/7858

Abstract: Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.

公开(公告)号：US09431540B2

公开(公告)日：2016-08-30

申请号：US14288766

申请日：2014-05-28

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US09406751B2

公开(公告)日：2016-08-02

申请号：US14296818

申请日：2014-06-05

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L27/12 ,  H01L29/786 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

Abstract translation: 提供一种制造半导体器件的方法。 在热处理之后，用拉伸应变诱导材料形成凸起的源极和漏极区域以形成源极漏极延伸区域，从而将应变诱导材料保持在期望的替代状态。

公开(公告)号：US20150380258A1

公开(公告)日：2015-12-31

申请号：US14314384

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L21/308 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights.

Abstract translation: 描述了形成翅片结构的方法和结构，同时在大面积上以高均匀性控制翅片结构的高度。 根据一些方面，在衬底上形成包括由衬底分离并通过间隔层彼此分离的第一蚀刻停止层和第二蚀刻停止层的多层结构。 沟槽可以通过第一和第二蚀刻停止层形成。 可以在沟槽中形成缓冲层，将沟槽填充到大致在第一蚀刻停止层的位置处的水平。 半导体层可以形成在缓冲层的上方并被回蚀刻到第二蚀刻停止层以形成高均匀高度的半导体鳍片。

公开(公告)号：US20150372104A1

公开(公告)日：2015-12-24

申请号：US14312418

申请日：2014-06-23

Applicant: STMICROELCTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/10 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是，当使用金属来形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分可以产生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。