In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.