公开(公告)号：US10248558B2

公开(公告)日：2019-04-02

申请号：US15690197

申请日：2017-08-29

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Rakesh Misra

IPC: G06F3/06 ,  G06F12/08 ,  G06F1/32 ,  G06F12/02 ,  G06F1/3206 ,  G06F1/3234 ,  G06F11/36 ,  H02H3/32

Abstract: In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.

公开(公告)号：US20190065359A1

公开(公告)日：2019-02-28

申请号：US15690197

申请日：2017-08-29

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Rakesh Misra

IPC: G06F12/02 ,  G06F1/32 ,  G06F11/36 ,  H02H3/32

Abstract: In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.

公开(公告)号：US10664006B2

公开(公告)日：2020-05-26

申请号：US15868211

申请日：2018-01-11

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Rakesh Misra ,  Rajesh Arimilli

IPC: G06F1/26 ,  G06F1/10 ,  G06F1/3234 ,  G06F1/3237

Abstract: Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.

公开(公告)号：US10466766B2

公开(公告)日：2019-11-05

申请号：US15808538

申请日：2017-11-09

Applicant: QUALCOMM Incorporated

Inventor： Rajesh Arimilli ,  Bharat Kumar Rangarajan ,  Rakesh Misra

IPC: G11C5/14 ,  G06F1/3234 ,  G06F1/3287 ,  G11C11/419 ,  G06F13/42 ,  G06F1/3206

Abstract: Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.

公开(公告)号：US10831667B2

公开(公告)日：2020-11-10

申请号：US16173221

申请日：2018-10-29

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Chulmin Jung ,  Rakesh Misra

IPC: G06F12/0846 ,  G06F12/0808 ,  G06F12/0891 ,  G06F12/0895

Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.

公开(公告)号：US11494248B2

公开(公告)日：2022-11-08

申请号：US16722861

申请日：2019-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： Rakesh Misra ,  Rohit Gupta ,  Shubham Maheshwari ,  Pawan Chhabra

IPC: G06F11/07 ,  G06F9/4401 ,  G06F15/78 ,  G06F1/24 ,  G06F11/14 ,  G06F11/30 ,  G06F1/3203

Abstract: A warm mission-mode reset may be performed in a portable computing device. Assertion of a signal indicating an error condition may be detected. In response to detection of the signal indicating an error condition, a signal indicating a request to preserve memory contents may be provided to a DRAM subsystem. Then, in response to a signal acknowledging the DRAM subsystem is preserving the memory contents, a system reset signal may be asserted.

公开(公告)号：US09886081B2

公开(公告)日：2018-02-06

申请号：US15010237

申请日：2016-01-29

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha Banerjee ,  Rakesh Misra

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: An apparatus includes a first circuit configured to receive one or more requests from a plurality of cores. Each of the one or more requests is to enter or to exit one of a plurality of power-down modes. The first circuit further selects one or more of the cores to enter or to exit the requested power-down mode or modes based on inrush current information associated with the power-down modes. A second circuit is configured to effect entering or exiting the requested power-down mode or modes in the selected one or more of the cores.