Invention Grant
- Patent Title: Methods of forming a protection layer on a semiconductor device and the resulting device
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Application No.: US15451565Application Date: 2017-03-07
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Publication No.: US10249726B2Publication Date: 2019-04-02
- Inventor: Ruilong Xie , Chanro Park , Xiuyu Cai
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/66 ; H01L29/78 ; H01L21/311 ; H01L21/768 ; H01L23/535 ; H01L29/423

Abstract:
One illustrative example of a transistor device disclosed herein includes, among other things, a gate structure, first and second spacers positioned adjacent opposite sides of the gate structure, and a multi-layer gate cap structure positioned above the gate structure and the upper surface of the spacers. The multi-layer gate cap structure includes a first gate cap material layer positioned on an upper surface of the gate structure and on the upper surfaces of the first and second spacers, a first high-k protection layer positioned on an upper surface of the first gate cap material layer and a second gate cap material layer positioned on an upper surface of the high-k protection layer. The first and second gate cap layers comprise different materials than the first high-k protection layer.
Public/Granted literature
- US20170179246A1 METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE Public/Granted day:2017-06-22
Information query
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