Invention Grant
- Patent Title: Scheduler to improve fairness and throughput for full-duplex WiFi communications
-
Application No.: US15471410Application Date: 2017-03-28
-
Publication No.: US10257108B2Publication Date: 2019-04-09
- Inventor: Yicong Wang , Shu-Ping Yeh , Ping Wang , Alexander W. Min , Yang-Seok Choi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H04W72/12
- IPC: H04W72/12 ; H04L5/14 ; H04L12/863 ; H04W88/08 ; H04W74/08 ; H04W84/12

Abstract:
A full-duplex (FD) capable access point (AP) of a wireless basic service set (BSS) that includes a plurality of stations (STAs) is configured to implement opportunistic FD downlink (DL) transmissions to a non-FD capable STA in the BSS when decoding uplink (UL) data from a UL STA in the BSS. While decoding the UL data, the AP selects a DL STA from a queue of DL STAs based on a predetermined FD DL transmission rate from the AP to the DL STA while the AP is decoding the UL data from the UL STA. The AP then causes an amount of data to be transmitted as an FD transmission to the selected DL STA while the processor is decoding the data from the UL STA.
Public/Granted literature
- US20180288789A1 SCHEDULER TO IMPROVE FAIRNESS AND THROUGHPUT FOR FULL-DUPLEX WIFI COMMUNICATIONS Public/Granted day:2018-10-04
Information query