Invention Grant
- Patent Title: Separate clock synchronous architecture
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Application No.: US15475328Application Date: 2017-03-31
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Publication No.: US10261539B2Publication Date: 2019-04-16
- Inventor: Jagdeep Bal , Ron Wade
- Applicant: Integrated Device Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Agency: Christopher P. Maiorana, PC
- Main IPC: G06F13/38
- IPC: G06F13/38 ; G06F1/06 ; G06F1/12 ; G06F1/08 ; G06F13/42

Abstract:
An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.
Public/Granted literature
- US20180284835A1 SEPARATE CLOCK SYNCHRONOUS ARCHITECTURE Public/Granted day:2018-10-04
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