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1.发明授权公开(公告)号：US09581973B1
公开(公告)日：2017-02-28
申请号：US15083831
申请日：2016-03-29
发明人： Pankaj Goyal , Jagdeep Bal , Stephen E. Aycock
CPC分类号： G04F5/04 , G04G3/02 , H03B5/32 , H03B5/364 , H03B2200/0082 , H03K5/15006
摘要： An integrated circuit comprising, a resonator, a first clock circuit for generating a first clock signal having a first frequency in response to the resonator, a second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit of the integrated circuit, using a shift register based state machine and utilizing the inertia of the resonator to smoothly transition between the two oscillators, to provide a dual mode clock output signal.
摘要翻译： 一种集成电路，包括谐振器，用于响应谐振器产生具有第一频率的第一时钟信号的第一时钟电路，用于响应谐振器产生具有第二频率的第二时钟信号的第二时钟电路，其中， 第二时钟信号的第二频率由可编程分频器和耦合到第一时钟电路和第二时钟电路的时钟模式控制电路确定，时钟模式控制电路用于在第一振荡器电路和第二时钟电路之间逐渐切换谐振器 振荡器电路，使用基于移位寄存器的状态机并利用谐振器的惯性在两个振荡器之间平滑地转换，以提供双模式时钟输出信号。
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公开(公告)号：US10261539B2
公开(公告)日：2019-04-16
申请号：US15475328
申请日：2017-03-31
发明人： Jagdeep Bal , Ron Wade
摘要： An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.
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公开(公告)号：US09369139B1
公开(公告)日：2016-06-14
申请号：US14622851
申请日：2015-02-14
发明人： Min Chu , Jagdeep Bal
CPC分类号： H03L7/0995 , H03B2200/009 , H03B2200/0094 , H03B2200/0096 , H03K3/013 , H03K3/0315 , H03L3/00 , H03L7/081 , H03L7/183 , H03L2207/06
摘要： Methods and apparatuses are described to reduce phase noise in a low noise fractional reference-injection phase locked loop (FRIPLL). The FRIPLL includes a ring voltage controlled oscillator (VCO). An output of the ring VCO is input to a fractional interpolative frequency divider (FIFD). A signal comparison circuit receives a reference clock signal and a further delayed output of the FIFD. The signal comparison circuit produces a control voltage signal in response to a phase difference between the reference clock signal and the further delayed output of the FIFD. The control voltage signal is input to the ring VCO to control a ring VCO frequency. An oscillator control circuit has a first input and a second input. The first input is a first delayed output of the FIFD. The second input is the reference clock signal. The oscillator control circuit generates a realignment signal which is used to realign a state transition in a ring VCO output signal to the reference clock signal when the ring VCO output signal is in a low state. Realignment occurs repeatedly at a frequency of the reference clock signal.
摘要翻译： 描述了在低噪声分数参考 - 注入锁相环（FRIPLL）中减少相位噪声的方法和装置。 FRIPLL包括一个环形压控振荡器（VCO）。 环形VCO的输出被输入到分数内插分频器（FIFD）。 信号比较电路接收FIFD的参考时钟信号和进一步延迟的输出。 信号比较电路响应于参考时钟信号和FIFD的进一步延迟输出之间的相位差产生控制电压信号。 控制电压信号被输入到环形VCO以控制环形VCO频率。 振荡器控制电路具有第一输入和第二输入。 第一个输入是FIFD的第一个延迟输出。 第二个输入是参考时钟信号。 当环形VCO输出信号处于低电平状态时，振荡器控制电路产生一个重新对准信号，该对准信号用于将环形VCO输出信号中的状态转换重新对准基准时钟信号。 在参考时钟信号的频率处重复对准。
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公开(公告)号：US10264542B2
公开(公告)日：2019-04-16
申请号：US15475648
申请日：2017-03-31
发明人： Jagdeep Bal , Elie Ayache , Eduard Van Keulen
摘要： An apparatus includes a first independently clocked device and one or more second independently clocked devices. The first independently clocked device may comprise a clock generator. The clock generator may be configured to generate a clock signal. The first independently clocked device may be configured to wirelessly broadcast a synchronization signal based on the clock signal. The one or more second independently clocked devices may each comprise respective clock generators. The one or more second independently clocked devices may (a) be configured to receive the synchronization signal from the first independently clocked device and (b) synchronize the respective clock generators to the clock signal of the first independently clocked device in response to the synchronization signal.
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公开(公告)号：US09362928B1
公开(公告)日：2016-06-07
申请号：US14794782
申请日：2015-07-08
发明人： Pankaj Goyal , Jagdeep Bal
CPC分类号： H03L7/081 , H03L7/0814 , H03L7/1976
摘要： A fractional N-frequency divider having a reduced fractional spurious output signal, which utilizes a multi-modulus frequency divider and an accumulator to generate a calibration-timing window that is used to calibrate two oscillator circuits and a phase compensation circuit. The calibrated phase compensation circuit is then used to mitigate the fractional spurs in the output signal of the fractional N-frequency divider. The fractional N-frequency divider may be implemented into a fractional N-frequency synthesizer.
摘要翻译： 具有减小的分数杂散输出信号的分数N分频器，其使用多模式分频器和累加器来产生用于校准两个振荡器电路和相位补偿电路的校准时序窗口。 然后使用校准的相位补偿电路来减轻分数N分频器的输出信号中的分数杂散。 分数N分频器可以被实现为分数N频率合成器。
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公开(公告)号：US08854086B1
公开(公告)日：2014-10-07
申请号：US13795828
申请日：2013-03-12
发明人： Jagdeep Bal , Cheng Wen Hsiao
CPC分类号： H03K3/012 , G06F1/08 , G06F1/3215 , G06F1/324 , G06F1/3278 , Y02D10/126 , Y02D10/157
摘要： Integrated circuit devices include first and second periodic signal generators and a power down detection circuit. The first periodic signal generator is configured to generate at least a first periodic signal having a first frequency at an output thereof and the second periodic signal generator is configured to generate a second periodic signal having a second frequency less than the first frequency at an output thereof. The power down detection circuit is configured to selectively provide one or the other of the first and second periodic signals to an output terminal of the integrated circuit device, in response to monitoring a status of a signal received at an input terminal of the integrated circuit device. This received signal reflects a power down status of an external device that receives the selected one of the first and second periodic signals.
摘要翻译： 集成电路装置包括第一和第二周期信号发生器和断电检测电路。 第一周期信号发生器被配置为在其输出处产生具有第一频率的至少第一周期性信号，并且第二周期信号发生器被配置为在其输出处产生具有小于第一频率的第二频率的第二周期信号 。 断电检测电路被配置为响应于监视在集成电路装置的输入端子处接收的信号的状态而选择性地将第一和第二周期信号中的一个或另一个提供给集成电路装置的输出端子 。 该接收到的信号反映了接收第一和第二周期信号中所选择的一个的外部设备的掉电状态。
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公开(公告)号：US10687293B2
公开(公告)日：2020-06-16
申请号：US16363116
申请日：2019-03-25
发明人： Jagdeep Bal , Elie Ayache , Eduard Van Keulen
摘要： A system includes a first device comprising a first clock generating circuit and a transmitter circuit, and a plurality of second devices, each comprising a respective receiver circuit and a respective second clock generating circuit. The first clock generating circuit may be configured to generate a first clock signal, which may provide internal clocking for the first device. The transmitter circuit may be configured to generate a synchronization signal in response to the first clock signal and wirelessly transmit a broadcast signal communicating only the synchronization signal. The respective receiver circuit may be configured to receive the broadcast signal and present a recovered synchronization signal to the respective second clock generating circuit. The respective second clock generating circuit may be configured to generate a respective intermediate clock signal, synchronize the respective intermediate clock signal with the recovered synchronization signal, and generate a respective second clock signal that provides internal clocking for the second device.
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公开(公告)号：US20190223128A1
公开(公告)日：2019-07-18
申请号：US16363116
申请日：2019-03-25
发明人： Jagdeep Bal , Elie Ayache , Eduard Van Keulen
CPC分类号： H04W56/0015 , H04L7/0008 , H04L7/04
摘要： A system includes a first device comprising a first clock generating circuit and a transmitter circuit, and a plurality of second devices, each comprising a respective receiver circuit and a respective second clock generating circuit. The first clock generating circuit may be configured to generate a first clock signal, which may provide internal clocking for the first device. The transmitter circuit may be configured to generate a synchronization signal in response to the first clock signal and wirelessly transmit a broadcast signal communicating only the synchronization signal. The respective receiver circuit may be configured to receive the broadcast signal and present a recovered synchronization signal to the respective second clock generating circuit. The respective second clock generating circuit may be configured to generate a respective intermediate clock signal, synchronize the respective intermediate clock signal with the recovered synchronization signal, and generate a respective second clock signal that provides internal clocking for the second device.
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公开(公告)号：US20180288718A1
公开(公告)日：2018-10-04
申请号：US15475648
申请日：2017-03-31
发明人： Jagdeep Bal , Elie Ayache , Eduard Van Keulen
CPC分类号： H04W56/0015 , H04L7/04
摘要： An apparatus includes a first independently clocked device and one or more second independently clocked devices. The first independently clocked device may comprise a clock generator. The clock generator may be configured to generate a clock signal. The first independently clocked device may be configured to wirelessly broadcast a synchronization signal based on the clock signal. The one or more second independently clocked devices may each comprise respective clock generators. The one or more second independently clocked devices may (a) be configured to receive the synchronization signal from the first independently clocked device and (b) synchronize the respective clock generators to the clock signal of the first independently clocked device in response to the synchronization signal.
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公开(公告)号：US20180284835A1
公开(公告)日：2018-10-04
申请号：US15475328
申请日：2017-03-31
发明人： Jagdeep Bal , Ron Wade
CPC分类号： G06F1/12 , G06F1/08 , G06F13/4291
摘要： An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.
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