Invention Grant
- Patent Title: Fail-safe input/output (IO) circuit
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Application No.: US15447230Application Date: 2017-03-02
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Publication No.: US10262722B2Publication Date: 2019-04-16
- Inventor: Prajkta Vyavahare , Rajat Chauhan , Siva Srinivas Kothamasu
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Priority: IN3758/CHE/2014 20140731
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C11/4093 ; G11C11/4074 ; H03K17/687 ; G06F13/10 ; G11C11/4094 ; G06F1/3296

Abstract:
The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.
Public/Granted literature
- US20170178714A1 Fail-Safe I/O to Achieve Ultra Low System Power Public/Granted day:2017-06-22
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