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公开(公告)号：US20240134776A1
公开(公告)日：2024-04-25
申请号：US18403293
申请日：2024-01-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Rajesh Kumar Vanga , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F11/36 , G06F9/4401 , G06F11/30 , G06F13/10
CPC classification number: G06F11/3656 , G06F9/4401 , G06F11/3048 , G06F13/102 , G06F2201/86 , G06F2213/0038
Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.
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公开(公告)号：US20230205672A1
公开(公告)日：2023-06-29
申请号：US17686348
申请日：2022-03-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Vanga Kumar Rajesh , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F11/36 , G06F9/4401 , G06F11/30 , G06F13/10
CPC classification number: G06F11/3656 , G06F9/4401 , G06F11/3048 , G06F13/102 , G06F2201/86 , G06F2213/0038
Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.
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公开(公告)号：US20170308724A1
公开(公告)日：2017-10-26
申请号：US15493973
申请日：2017-04-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Siva Srinivas Kothamasu , Haydar Bilhan
IPC: G06K7/00 , G06K19/077
CPC classification number: G06K7/0013 , G06F1/26 , G11C5/14 , G11C5/147
Abstract: This invention is an SOC with an integrated single rail power supply that interfaces with the host controller and dynamically changes the host interface supply to 3.3 volts or 1.8 volts based on the sensed card speed grade. The SOC initially selects 3.3 volts to supply to the memory card. The SOC communicates with memory card vis input/output circuits to determine a memory type. The controller selects a 3.3 volt or 1.8 volt supply for the memory card based upon the determination. The SOC powers the input/output circuits at the same supply voltage as the memory card. This invention employes 1.8 volt transistors in the input/output circuits using a bias voltage to protect these transistor from the full 3.3 volt power when the memory card is powered to 3.3 volts.
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公开(公告)号：US09627035B2
公开(公告)日：2017-04-18
申请号：US15236797
申请日：2016-08-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prajkta Vyavahare , Rajat Chauhan , Siva Srinivas Kothamasu
IPC: G11C7/10 , G11C11/4093 , G11C11/4094 , G11C11/4074 , G06F13/10
CPC classification number: G11C11/4093 , G06F1/3296 , G06F13/102 , G11C7/1057 , G11C11/4074 , G11C11/4094 , H03K17/687 , Y02D10/14
Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.
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公开(公告)号：US20150362987A1
公开(公告)日：2015-12-17
申请号：US14304795
申请日：2014-06-13
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171 , Y02D10/172
Abstract: A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode. The power manager is arranged to selectively apply power to various voltage domains in response to the type of power mode selected. The processor is optionally arranged to signal the power manager of transitions to the selected suspend mode and of transitions to an active mode using a power enable signal.
Abstract translation: 例如，具有多个功率模式类型的系统包括功率管理器，该功率管理器响应于在处理器处于所选择的挂起模式时在易失性存储器中维持处理器上下文信息的暂停功率模式类型的选择。 状态寄存器被布置成在处理器处于选择的挂起电源模式时将上下文信息的状态保持在易失性存储器中。 功率管理器被布置为响应于所选择的功率模式的类型选择性地向各个电压域施加功率。 处理器可选地布置成使用功率使能信号向功率管理器发信号通知转换到所选择的暂停模式和转换到活动模式。
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Patent Agency Ranking
公开(公告)号：US20220365849A1
公开(公告)日：2022-11-17
申请号：US17878149
申请日：2022-08-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Siva Srinivas Kothamasu
Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.
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公开(公告)号：US10262722B2
公开(公告)日：2019-04-16
申请号：US15447230
申请日：2017-03-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prajkta Vyavahare , Rajat Chauhan , Siva Srinivas Kothamasu
IPC: G11C7/10 , G11C11/4093 , G11C11/4074 , H03K17/687 , G06F13/10 , G11C11/4094 , G06F1/3296
Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.
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公开(公告)号：US20180314590A1
公开(公告)日：2018-11-01
申请号：US15961010
申请日：2018-04-24
Applicant: Texas Instruments Incorporated
Inventor： Siva Srinivas Kothamasu
Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.
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公开(公告)号：US20170178714A1
公开(公告)日：2017-06-22
申请号：US15447230
申请日：2017-03-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prajkta Vyavahare , Rajat Chauhan , Siva Srinivas Kothamasu
IPC: G11C11/4093 , G06F1/32 , G06F13/10 , G11C11/4094 , G11C11/4074
CPC classification number: G11C11/4093 , G06F1/3296 , G06F13/102 , G11C7/1057 , G11C11/4074 , G11C11/4094 , H03K17/687 , Y02D10/14
Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.
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公开(公告)号：US11899563B2
公开(公告)日：2024-02-13
申请号：US17686348
申请日：2022-03-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Rajesh Kumar Vanga , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F13/10 , G06F11/36 , G06F9/4401 , G06F11/30
CPC classification number: G06F11/3656 , G06F9/4401 , G06F11/3048 , G06F13/102 , G06F2201/86 , G06F2213/0038
Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.
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