In a display controller, output surface data from a composition processing stage 22 is received by and stored in a local latency hiding buffer 40 of a memory write subsystem 31 before being written out to an external memory. The local buffer 40 of the memory write subsystem 31 signals when it is “full”, and in response thereto the inputting of output surface data to the local buffer 40 is stopped until the current line of the output surface has been finished, and then started again when the next line of the output surface begins. The writing of any data for the line of the output surface that was being written to the local buffer 40 that is already present in the local buffer 40 and not yet written to the external memory is also skipped, and it is recorded that the output surface line in question is not properly stored in the external memory.