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    Method of and apparatus for controlling overrun when writing data from a display controller to memory
    1.
    发明授权
    Method of and apparatus for controlling overrun when writing data from a display controller to memory 有权

    公开(公告)号：US10276125B2

    公开(公告)日：2019-04-30

    申请号：US15281451

    申请日：2016-09-30

    Applicant: ARM Limited

    Inventor： Piotr Tadeusz Chrobak ,  Michal Karol Bogusz

    IPC: G06F5/14 ,  G06F5/06 ,  G09G5/393 ,  G09G5/00 ,  G06F3/14 ,  G09G5/14 ,  G09G5/397

    Abstract: In a display controller, output surface data from a composition processing stage 22 is received by and stored in a local latency hiding buffer 40 of a memory write subsystem 31 before being written out to an external memory. The local buffer 40 of the memory write subsystem 31 signals when it is “full”, and in response thereto the inputting of output surface data to the local buffer 40 is stopped until the current line of the output surface has been finished, and then started again when the next line of the output surface begins. The writing of any data for the line of the output surface that was being written to the local buffer 40 that is already present in the local buffer 40 and not yet written to the external memory is also skipped, and it is recorded that the output surface line in question is not properly stored in the external memory.

    DISPLAY CONTROLLERS
    2.
    发明申请
    DISPLAY CONTROLLERS 审中-公开

    公开(公告)号：US20180095677A1

    公开(公告)日：2018-04-05

    申请号：US15281451

    申请日：2016-09-30

    Applicant: ARM Limited

    Inventor： Piotr Tadeusz Chrobak ,  Michal Karol Bogusz

    IPC: G06F3/06 ,  G06T1/20 ,  G06T1/60 ,  G09G5/00

    CPC classification number: G09G5/001 ,  G06F3/14 ,  G06F5/06 ,  G06F5/14 ,  G09G5/14 ,  G09G5/393 ,  G09G5/397 ,  G09G2340/12

    Abstract: In a display controller, output surface data from a composition processing stage 22 is received by and stored in a local latency hiding buffer 40 of a memory write subsystem 31 before being written out to an external memory. The local buffer 40 of the memory write subsystem 31 signals when it is “full”, and in response thereto the inputting of output surface data to the local buffer 40 is stopped until the current line of the output surface has been finished, and then started again when the next line of the output surface begins. The writing of any data for the line of the output surface that was being written to the local buffer 40 that is already present in the local buffer 40 and not yet written to the external memory is also skipped, and it is recorded that the output surface line in question is not properly stored in the external memory.

    Prefetching page access data for input surfaces requiring processing
    3.
    发明授权
    Prefetching page access data for input surfaces requiring processing 有权

    公开(公告)号：US10593305B2

    公开(公告)日：2020-03-17

    申请号：US15361751

    申请日：2016-11-28

    Applicant: ARM Limited

    Inventor： Michal Karol Bogusz ,  Damian Piotr Modrzyk ,  Quinn Carter ,  Thomas James Cooksey

    IPC: G06F12/0862 ,  G06F12/0875 ,  G06F12/1027 ,  G06T1/60 ,  G09G5/397 ,  G09G5/36 ,  G09G5/395 ,  G06T15/00

    Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller.The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.

    De-interlacing data arrays in data processing systems
    5.
    发明授权
    De-interlacing data arrays in data processing systems 有权

    公开(公告)号：US10659723B2

    公开(公告)日：2020-05-19

    申请号：US15810090

    申请日：2017-11-12

    Applicant: Arm Limited

    Inventor： Michal Karol Bogusz ,  Piotr Tadeusz Chrobak

    IPC: H04N7/01 ,  G09G5/00 ,  G06T3/40 ,  H04N5/262

    Abstract: A data processing system includes a scaler 18 operable to scale a received input data array to provide a scaled output version of the input data array. When it is desired to produce a de-interlaced and scaled output version of an input data array 21, 22, the input data array 21, 22 is provided to the scaler 18, and the scaler 18 scales the input data array 21, 22 so as to simultaneously de-interlace and scale the input data array and to produce a de-interlaced and scaled output version of the input data array.

    Apparatus and method for performing address translation
    6.
    发明授权
    Apparatus and method for performing address translation 有权

    公开(公告)号：US10255195B2

    公开(公告)日：2019-04-09

    申请号：US15614644

    申请日：2017-06-06

    Applicant: ARM LIMITED

    Inventor： Michal Karol Bogusz ,  Quinn Carter ,  Andrew Brookfield Swaine

    IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/02 ,  G06F12/1009

    Abstract: An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.

    Data processing systems
    8.
    发明授权
    Data processing systems 有权

    公开(公告)号：US10395339B2

    公开(公告)日：2019-08-27

    申请号：US15636890

    申请日：2017-06-29

    Applicant: ARM Limited

    Inventor： Michal Karol Bogusz ,  Tomasz Jan Pabis

    IPC: G06T3/00 ,  G06T3/40 ,  G06T7/136

    Abstract: In a data processing system, an input data array to be downscaled is split into plural parts along its horizontal extent and the different parts of the input data array are then provided to respective scalers of the data processing system and are respectively downscaled by those scalers to provide a plurality of downscaled output parts. The plural downscaled output parts are then combined (merged) to provide the desired downscaled output data array.

    DATA PROCESSING SYSTEMS
    10.
    发明申请
    DATA PROCESSING SYSTEMS 审中-公开

    公开(公告)号：US20170162179A1

    公开(公告)日：2017-06-08

    申请号：US15361751

    申请日：2016-11-28

    Applicant: ARM Limited

    Inventor： Michal Karol Bogusz ,  Damian Piotr Modrzyk ,  Quinn Carter ,  Thomas James Cooksey

    IPC: G09G5/397 ,  G09G5/36 ,  G06F12/1027 ,  G06F12/0862 ,  G06F12/0875

    Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller.The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.

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