Invention Grant
- Patent Title: Test partition external input/output interface control for test partitions in a semiconductor
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Application No.: US15336687Application Date: 2016-10-27
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Publication No.: US10281524B2Publication Date: 2019-05-07
- Inventor: Sailendra Chadalavda , Shantanu Sarangi , Milind Sonawane , Amit Sanghani , Jonathon E. Colburn , Dan Smith , Jue Wu , Mahmut Yilmaz
- Applicant: NVIDIA CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/26 ; G01R31/317 ; G01R31/28 ; G01R31/3185 ; G06F11/00

Abstract:
In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.
Public/Granted literature
- US20170115338A1 TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL Public/Granted day:2017-04-27
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