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    GRANULAR DYNAMIC TEST SYSTEMS AND METHODS
    2.
    发明申请
    GRANULAR DYNAMIC TEST SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20170115353A1

    公开(公告)日：2017-04-27

    申请号：US15336716

    申请日：2016-10-27

    Applicant: NVIDIA CORPORATION

    Inventor： Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Bala Tarun Nelapatla ,  Shantanu Sarangi ,  Rajendra Kumar reddy.S

    IPC: G01R31/317 ,  G01R31/3177

    Abstract: In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

    Granular dynamic test systems and methods
    3.
    发明授权
    Granular dynamic test systems and methods 有权

    公开(公告)号：US10545189B2

    公开(公告)日：2020-01-28

    申请号：US15336716

    申请日：2016-10-27

    Applicant: NVIDIA CORPORATION

    Inventor： Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Bala Tarun Nelapatla ,  Shantanu Sarangi ,  Rajendra Kumar reddy.S ,  Sailendra Chadalavada

    IPC: G01R31/3177 ,  G01R31/26 ,  G01R31/3185 ,  G06F11/00 ,  G01R31/317 ,  G01R31/28

    Abstract: In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

    Performing on-chip partial good die identification
    9.
    发明授权
    Performing on-chip partial good die identification 有权

    公开(公告)号：US09829536B2

    公开(公告)日：2017-11-28

    申请号：US15015100

    申请日：2016-02-03

    Applicant: NVIDIA Corporation

    Inventor： Milind Sonawane ,  Jonathon E. Colburn ,  Amit Sanghani

    IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/31703 ,  G01R31/3177 ,  G01R31/31835

    Abstract: In one embodiment, a multiple input signature register (MISR) shadow works with a MISR to compress test responses of a layout partition in a functional region of an integrated circuit. In operation, for each test pattern in a test pattern split, the MISR generates a MISR signature based on the responses of the layout partition. As the test patterns in the test pattern split execute, the MISR shadow accumulates the MISR signatures and stores the result as MISR shadow data. After the final test pattern included in the test pattern split executes, the MISR shadow combines the bits in the MISR shadow data to form a single bit MISR shadow status that indicates whether the layout partition, and therefore the functional region, responds properly to the test pattern split. By efficiently summarizing the test responses, the MISR shadow optimizes the resources required to identify defective functional regions.

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