中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.017 seconds)

    Granular dynamic test systems and methods
    1.
    发明授权
    Granular dynamic test systems and methods 有权

    公开(公告)号：US10545189B2

    公开(公告)日：2020-01-28

    申请号：US15336716

    申请日：2016-10-27

    Applicant: NVIDIA CORPORATION

    Inventor： Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Bala Tarun Nelapatla ,  Shantanu Sarangi ,  Rajendra Kumar reddy.S ,  Sailendra Chadalavada

    IPC: G01R31/3177 ,  G01R31/26 ,  G01R31/3185 ,  G06F11/00 ,  G01R31/317 ,  G01R31/28

    Abstract: In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

    Scan systems and methods
    2.
    发明授权
    Scan systems and methods 有权

    公开(公告)号：US09885753B2

    公开(公告)日：2018-02-06

    申请号：US14050242

    申请日：2013-10-09

    Applicant: Nvidia Corporation

    Inventor： Amit Sanghani ,  Farideh Golshan ,  Venkata Kottapalli ,  Milind Sonawane ,  Ketan Kulkarni

    IPC: G01R31/3185 ,  G01R31/3177

    CPC classification number: G01R31/318586 ,  G01R31/3177

    Abstract: Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row.

    Global low power capture scheme for cores
    4.
    发明授权
    Global low power capture scheme for cores 有权
    用于核心的全球低功耗捕获方案

    公开(公告)号：US09222981B2

    公开(公告)日：2015-12-29

    申请号：US13730690

    申请日：2012-12-28

    Applicant: NVIDIA Corporation

    Inventor： Satya Puvvada ,  Milind Sonawane ,  Amit D Sanghani ,  Anubhav Sinha ,  Vishal Agarwal

    IPC: G01R31/28 ,  G01R31/3185

    CPC classification number: G01R31/318544 ,  G01R31/318575

    Abstract: A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.

    Abstract translation: 提出了一种在扫描捕获模式下测试集成电路以减少峰值功率问题的方法。 该方法包括为集成电路中的多个核心和高速缓冲存储器中的每一个编程相应的第一时间窗口的持续时间。 它还包括对于多个核心和高速缓存中的每一个的第一时间窗口期间对第一时钟信号的脉冲数进行计数。 随后，该方法包括通过在相应的第二时间窗口期间为多个核心和高速缓冲存储器中的每一个生成第二时钟信号的脉冲，向多个核心和高速缓冲存储器交错捕获脉冲，其中产生的脉冲数目基于 为多个核心和高速缓存中的每一个计数的第一时钟信号脉冲的相应数目。

    DYNAMIC INDEPENDENT TEST PARTITION CLOCK
    7.
    发明申请
    DYNAMIC INDEPENDENT TEST PARTITION CLOCK 审中-公开

    公开(公告)号：US20170115351A1

    公开(公告)日：2017-04-27

    申请号：US15336626

    申请日：2016-10-27

    Applicant: NVIDIA CORPORATION

    Inventor： Pavan Kumar Datla Jagannadha ,  Dheepakkumaran Jayaraman ,  Anubhav Sinha ,  Karthikeyan Natarajan ,  Shantanu Sarangi ,  Amit Sanghani ,  Milind Sonawane ,  Mahmut Yilmaz

    IPC: G01R31/317 ,  G01R31/3177

    Abstract: In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

    System for reducing peak power during scan shift at the global level for scan based tests
    9.
    发明授权
    System for reducing peak power during scan shift at the global level for scan based tests 有权
    用于在扫描测试的全局级别扫描移位期间降低峰值功率的系统

    公开(公告)号：US09377510B2

    公开(公告)日：2016-06-28

    申请号：US13730628

    申请日：2012-12-28

    Applicant: NVIDIA Corporation

    Inventor： Milind Sonawane ,  Satya Puvvada ,  Amit Sanghani

    IPC: G01R31/28 ,  G06F11/00 ,  G06F1/12 ,  G01R31/3185

    CPC classification number: G01R31/318552 ,  G01R31/318575

    Abstract: A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.

    Abstract translation: 提出了一种在扫描移位周期中降低峰值功率的方法。 该方法包括在时钟树根的集成电路上复用测试时钟与功能时钟。 该方法还包括在时钟路径上添加多个延迟元件，其中时钟路径是由多路复用产生的信号。 此外，该方法包括将时钟路径路由到集成电路上的多个核和高速缓存（例如L2C高速缓存）。 最后，该方法包括通过在扫描移位周期期间采用延迟元件来交错由多个核心和高速缓存中的每一个接收的测试时钟。

Patent Agency Ranking