Invention Grant
- Patent Title: Molded package with chip carrier comprising brazed electrically conductive layers
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Application No.: US16111606Application Date: 2018-08-24
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Publication No.: US10283432B2Publication Date: 2019-05-07
- Inventor: Mark Pavier , Wolfram Hable , Angela Kessler , Michael Sielaff , Anton Pugatschow , Charles Rimbert-Riviere , Marco Sobkowiak
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Priority: EP17290085 20170702
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/373 ; B60R16/02 ; H01L21/56 ; H01L25/18 ; H01L23/29 ; H01L23/00 ; H01L23/498 ; H01L23/50 ; H01L23/31

Abstract:
A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
Public/Granted literature
- US20190006260A1 Molded package with chip carrier comprising brazed electrically conductive layers Public/Granted day:2019-01-03
Information query
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