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公开(公告)号:US10573611B2
公开(公告)日:2020-02-25
申请号:US16163006
申请日:2018-10-17
Applicant: Infineon Technologies AG
Inventor: Kamil Karlovsky , Evelyn Napetschnig , Michael Ehmann , Mark James Harrison , Anton Pugatschow
IPC: H01L23/00 , H01L21/683
Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
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公开(公告)号:US20190051624A1
公开(公告)日:2019-02-14
申请号:US16163006
申请日:2018-10-17
Applicant: Infineon Technologies AG
Inventor: Kamil Karlovsky , Evelyn Napetschnig , Michael Ehmann , Mark James Harrison , Anton Pugatschow
IPC: H01L23/00
Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
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公开(公告)号:US10074590B1
公开(公告)日:2018-09-11
申请号:US15649459
申请日:2017-07-13
Applicant: Infineon Technologies AG
Inventor: Mark Pavier , Wolfram Hable , Angela Kessler , Michael Sielaff , Anton Pugatschow , Charles Rimbert-Riviere , Marco Sobkowiak
IPC: H01L23/498 , H01L23/373 , H01L23/31 , H01L23/50 , H01L23/00 , H01L23/29 , H01L25/18 , H01L21/48 , H01L21/56 , B60R16/02
CPC classification number: H01L23/3735 , B60R16/02 , H01L21/4807 , H01L21/4825 , H01L21/565 , H01L23/15 , H01L23/293 , H01L23/3107 , H01L23/3114 , H01L23/49524 , H01L23/49531 , H01L23/49541 , H01L23/49555 , H01L23/49861 , H01L23/50 , H01L24/45 , H01L24/48 , H01L25/18 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/45565 , H01L2224/45624 , H01L2224/48139 , H01L2224/48175 , H01L2224/4846 , H01L2924/00014 , H01L2924/1203 , H01L2924/13055 , H01L2924/14252 , H01L2924/181 , H01L2924/2076 , H01L2924/00012 , H01L2924/206 , H01L2224/43848
Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.
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公开(公告)号:US10283432B2
公开(公告)日:2019-05-07
申请号:US16111606
申请日:2018-08-24
Applicant: Infineon Technologies AG
Inventor: Mark Pavier , Wolfram Hable , Angela Kessler , Michael Sielaff , Anton Pugatschow , Charles Rimbert-Riviere , Marco Sobkowiak
IPC: H01L21/48 , H01L23/373 , B60R16/02 , H01L21/56 , H01L25/18 , H01L23/29 , H01L23/00 , H01L23/498 , H01L23/50 , H01L23/31
Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
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公开(公告)号:US10115688B2
公开(公告)日:2018-10-30
申请号:US14726078
申请日:2015-05-29
Applicant: Infineon Technologies AG
Inventor: Kamil Karlovsky , Evelyn Napetschnig , Michael Ehmann , Mark Harrison , Anton Pugatschow
Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
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公开(公告)号:US20160351516A1
公开(公告)日:2016-12-01
申请号:US14726078
申请日:2015-05-29
Applicant: Infineon Technologies AG
Inventor: Kamil Karlovsky , Evelyn Napetschnig , Michael Ehmann , Mark Harrison , Anton Pugatschow
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/83 , H01L2224/0401 , H01L2224/0558 , H01L2224/05599 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/04953
Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.
Abstract translation: 半导体器件包括设置在衬底的半导体表面上的接触金属层,设置在接触金属层上的扩散阻挡层,设置在扩散阻挡层上的惰性层和设置在惰性层上的焊料层。
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公开(公告)号:US20150228607A1
公开(公告)日:2015-08-13
申请号:US14692815
申请日:2015-04-22
Applicant: Infineon Technologies AG
Inventor: Tobias Schmidt , Evelyn Napetschnig , Franz Stueckler , Anton Pugatschow , Mark Harrison
IPC: H01L23/00
CPC classification number: H01L24/32 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/83 , H01L2224/0345 , H01L2224/03452 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/0516 , H01L2224/05164 , H01L2224/05166 , H01L2224/0517 , H01L2224/05171 , H01L2224/05172 , H01L2224/05179 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/06181 , H01L2224/29082 , H01L2224/32227 , H01L2224/83805 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/10335 , H01L2924/10337 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/00
Abstract: In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process.
Abstract translation: 在各种实施例中,提供层叠。 层叠可以包括载体; 设置在载体上的第一金属; 设置在所述第一金属上的第二金属; 以及设置在第二金属上方的焊料材料或提供与由外部源供应的焊料的接触的材料。 第二金属可以具有至少1800℃的熔融温度,并且在焊接工艺期间和焊接工艺之后至少一个焊料材料中不会或基本上不溶解。
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