公开(公告)号：US10074590B1

公开(公告)日：2018-09-11

申请号：US15649459

申请日：2017-07-13

Applicant: Infineon Technologies AG

Inventor： Mark Pavier ,  Wolfram Hable ,  Angela Kessler ,  Michael Sielaff ,  Anton Pugatschow ,  Charles Rimbert-Riviere ,  Marco Sobkowiak

IPC: H01L23/498 ,  H01L23/373 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H01L23/29 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  B60R16/02

CPC classification number: H01L23/3735 ,  B60R16/02 ,  H01L21/4807 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/15 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45624 ,  H01L2224/48139 ,  H01L2224/48175 ,  H01L2224/4846 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/14252 ,  H01L2924/181 ,  H01L2924/2076 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/43848

Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.

公开(公告)号：US10283432B2

公开(公告)日：2019-05-07

申请号：US16111606

申请日：2018-08-24

Applicant: Infineon Technologies AG

Inventor： Mark Pavier ,  Wolfram Hable ,  Angela Kessler ,  Michael Sielaff ,  Anton Pugatschow ,  Charles Rimbert-Riviere ,  Marco Sobkowiak

IPC: H01L21/48 ,  H01L23/373 ,  B60R16/02 ,  H01L21/56 ,  H01L25/18 ,  H01L23/29 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  H01L23/31

Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.