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1.发明申请公开(公告)号：US20140204536A1
公开(公告)日：2014-07-24
申请号：US14161246
申请日：2014-01-22
Applicant: Infineon Technologies AG
Inventor： Patrick Jones , Christoph Koch , Michael Sielaff
CPC classification number: H05K7/02 , H01L2924/0002 , H05K7/1432 , H05K7/20409 , H05K7/209 , Y10T29/41 , H01L2924/00
Abstract: A semiconductor module arrangement is provided having a first subassembly, a second subassembly and a third subassembly. The third subassembly has a quantity of adjustment pins which are fixedly connected to one another. The first subassembly has a number N1 of first adjustment openings, and the second subassembly has a number N2 of second adjustment openings. Each of the adjustment pins engages into a different one of the first adjustment openings and/or into one of the second adjustment openings. A corresponding method of producing the semiconductor module arrangement is also provided.
Abstract translation: 提供了具有第一子组件，第二子组件和第三子组件的半导体模块布置。 第三子组件具有彼此固定连接的一定数量的调节销。 第一子组件具有N1的第一调节开口，第二子组件具有N2的第二调节开口。 每个调节销接合到第一调节开口中的不同一个和/或第二调节开口中的一个。 还提供了制造半导体模块装置的相应方法。
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公开(公告)号：US11596077B2
公开(公告)日：2023-02-28
申请号：US15858970
申请日：2017-12-29
Applicant: Infineon Technologies AG
Inventor： Patrick Jones , Christoph Koch , Michael Sielaff
Abstract: A method of producing a semiconductor module arrangement includes providing a first subassembly having a number N1 of first adjustment openings, a second subassembly having a number N2 of second adjustment openings and a third subassembly having a plurality of adjustment pins which are fixedly connected to one another, the first subassembly, the second subassembly and the third subassembly being independent of one another and not connected to one another. The first subassembly, the second subassembly and the third subassembly are arranged relative to one another in such a way that each of the adjustment pins engages into one of the first adjustment openings and/or into one of the second adjustment openings.
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公开(公告)号：USD762185S1
公开(公告)日：2016-07-26
申请号：US29518151
申请日：2015-02-20
Applicant: Infineon Technologies AG
Designer： Jutta Muehlensiep , Michael Sielaff
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Patent Agency Ranking
公开(公告)号：US10283432B2
公开(公告)日：2019-05-07
申请号：US16111606
申请日：2018-08-24
Applicant: Infineon Technologies AG
Inventor： Mark Pavier , Wolfram Hable , Angela Kessler , Michael Sielaff , Anton Pugatschow , Charles Rimbert-Riviere , Marco Sobkowiak
IPC: H01L21/48 , H01L23/373 , B60R16/02 , H01L21/56 , H01L25/18 , H01L23/29 , H01L23/00 , H01L23/498 , H01L23/50 , H01L23/31
Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
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公开(公告)号：US10074590B1
公开(公告)日：2018-09-11
申请号：US15649459
申请日：2017-07-13
Applicant: Infineon Technologies AG
Inventor： Mark Pavier , Wolfram Hable , Angela Kessler , Michael Sielaff , Anton Pugatschow , Charles Rimbert-Riviere , Marco Sobkowiak
IPC: H01L23/498 , H01L23/373 , H01L23/31 , H01L23/50 , H01L23/00 , H01L23/29 , H01L25/18 , H01L21/48 , H01L21/56 , B60R16/02
CPC classification number: H01L23/3735 , B60R16/02 , H01L21/4807 , H01L21/4825 , H01L21/565 , H01L23/15 , H01L23/293 , H01L23/3107 , H01L23/3114 , H01L23/49524 , H01L23/49531 , H01L23/49541 , H01L23/49555 , H01L23/49861 , H01L23/50 , H01L24/45 , H01L24/48 , H01L25/18 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/45565 , H01L2224/45624 , H01L2224/48139 , H01L2224/48175 , H01L2224/4846 , H01L2924/00014 , H01L2924/1203 , H01L2924/13055 , H01L2924/14252 , H01L2924/181 , H01L2924/2076 , H01L2924/00012 , H01L2924/206 , H01L2224/43848
Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.
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公开(公告)号：US20180146566A1
公开(公告)日：2018-05-24
申请号：US15858970
申请日：2017-12-29
Applicant: Infineon Technologies AG
Inventor： Patrick Jones , Christoph Koch , Michael Sielaff
CPC classification number: H05K7/02 , H01L2924/0002 , H05K7/1432 , H05K7/20409 , H05K7/209 , H01L2924/00
Abstract: A method of producing a semiconductor module arrangement includes providing a first subassembly having a number N1 of first adjustment openings, a second subassembly having a number N2 of second adjustment openings and a third subassembly having a plurality of adjustment pins which are fixedly connected to one another, the first subassembly, the second subassembly and the third subassembly being independent of one another and not connected to one another. The first subassembly, the second subassembly and the third subassembly are arranged relative to one another in such a way that each of the adjustment pins engages into one of the first adjustment openings and/or into one of the second adjustment openings.
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7.发明授权公开(公告)号：US09888601B2
公开(公告)日：2018-02-06
申请号：US14161246
申请日：2014-01-22
Applicant: Infineon Technologies AG
Inventor： Patrick Jones , Christoph Koch , Michael Sielaff
CPC classification number: H05K7/02 , H01L2924/0002 , H05K7/1432 , H05K7/20409 , H05K7/209 , Y10T29/41 , H01L2924/00
Abstract: A semiconductor module arrangement is provided having a first subassembly, a second subassembly and a third subassembly. The third subassembly has a quantity of adjustment pins which are fixedly connected to one another. The first subassembly has a number N1 of first adjustment openings, and the second subassembly has a number N2 of second adjustment openings. Each of the adjustment pins engages into a different one of the first adjustment openings and/or into one of the second adjustment openings. A corresponding method of producing the semiconductor module arrangement is also provided.
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公开(公告)号：US20160113123A1
公开(公告)日：2016-04-21
申请号：US14886818
申请日：2015-10-19
Applicant: Infineon Technologies AG
Inventor： Patrick Jones , Christoph Koch , Michael Sielaff
CPC classification number: B23K1/0016 , B23K3/087 , B23K2101/36 , H01L23/13 , H01L23/15 , H01L23/36 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32225 , H01L2224/83424 , H01L2224/83447 , H01L2224/83455 , H01L2224/83825 , H01L2224/8384 , H01L2224/8385 , H01L2224/83851 , H05K1/0306 , H05K3/0061 , H05K2201/09054 , H05K2201/10166 , H05K2203/0405 , H05K2203/167 , H01L2924/00014 , H01L2924/014 , H01L2924/07802 , H01L2924/0781
Abstract: A method for soldering a circuit carrier to a carrier plate includes providing a carrier plate having an upper side and a first adjusting device, providing a circuit carrier having an underside and a second adjusting device, providing a solder and placing the circuit carrier onto the carrier plate in such a way that: the underside of the circuit carrier faces the upper side of the carrier plate; the solder is arranged between the carrier plate and the circuit carrier; and the first adjusting device forms a stop for the second adjusting device that limits a displacement of the circuit carrier placed on the carrier plate along the upper side of the carrier plate. After placing the circuit carrier onto the carrier plate, the solder is melted and subsequently cooled down until it solidifies and connects the circuit carrier to the carrier plate in a material-bonding manner at a lower metallization layer.
Abstract translation: 将电路载体焊接到载体板的方法包括提供具有上侧和第一调节装置的载体板，提供具有下侧的电路载体和第二调节装置，提供焊料并将电路载体放置在载体上 板的方式为：电路载体的下侧面向承载板的上侧; 焊料布置在载体板和电路载体之间; 并且第一调节装置形成用于第二调节装置的止动件，其限制沿承载板的上侧放置在承载板上的电路载体的位移。 在将电路载体放置在载体板上之后，焊料熔化并随后冷却直到其固化并且在下部金属化层处以材料粘合方式将电路载体固定到载体板上。
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