Invention Grant
- Patent Title: Interconnect routing configurations and associated techniques
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Application No.: US15297005Application Date: 2016-10-18
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Publication No.: US10283453B2Publication Date: 2019-05-07
- Inventor: Zhiguo Qian , Kemal Aygun , Dae-Woo Kim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/538 ; G06F17/50 ; H01L21/48 ; H01L25/065 ; H01L23/00

Abstract:
Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20170040264A1 INTERCONNECT ROUTING CONFIGURATIONS AND ASSOCIATED TECHNIQUES Public/Granted day:2017-02-09
Information query
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