- Patent Title: Method and apparatus for improving sequential reading in NAND flash
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Application No.: US15195452Application Date: 2016-06-28
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Publication No.: US10289313B2Publication Date: 2019-05-14
- Inventor: Han Liu , Shantanu R. Rajwade , Pranav Kalavade
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F1/24
- IPC: G06F1/24 ; G06F3/06 ; G11C11/56 ; G11C7/06 ; G11C16/04 ; G11C16/08 ; G11C16/32

Abstract:
In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a read request from a computing host; identify a plurality of pages specified by the read request that are stored in the same group of memory cells of the NAND flash memory, wherein each memory cell of the group of memory cells is to store a bit of each of the plurality of identified pages; and read, in a single read cycle, the plurality of pages from the group of memory cells of the NAND flash memory.
Public/Granted literature
- US20170371565A1 METHOD AND APPARATUS FOR IMPROVING SEQUENTIAL READING IN NAND FLASH Public/Granted day:2017-12-28
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