Invention Grant
- Patent Title: Data coherency model and protocol at cluster level
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Application No.: US15178159Application Date: 2016-06-09
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Publication No.: US10296399B2Publication Date: 2019-05-21
- Inventor: Debendra Das Sharma , Mohan J. Kumar , Balint Fleischer
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F9/52 ; G06F3/06 ; G06F11/20 ; G06F13/32 ; G06F12/0815 ; G06F9/46 ; G06F12/1081 ; G06F13/16 ; G06F13/40 ; G11C14/00 ; G06F12/0817

Abstract:
An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
Public/Granted literature
- US20170046208A1 DATA COHERENCY MODEL AND PROTOCOL AT CLUSTER LEVEL Public/Granted day:2017-02-16
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