Invention Grant
- Patent Title: NAND boosting using dynamic ramping of word line voltages
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Application No.: US15352390Application Date: 2016-11-15
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Publication No.: US10297329B2Publication Date: 2019-05-21
- Inventor: Peter Rabkin , Yingda Dong , Masaaki Higashitani
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/10 ; G11C11/56 ; G11C16/04

Abstract:
Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.
Public/Granted literature
- US20170062068A1 NAND Boosting Using Dynamic Ramping of Word Line Voltages Public/Granted day:2017-03-02
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