公开(公告)号：US11676954B2

公开(公告)日：2023-06-13

申请号：US17134997

申请日：2020-12-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani ,  Kwang-ho Kim

IPC: H01L25/065 ,  H01L23/528 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L25/18 ,  H01L23/5286 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers; memory openings extending through the alternating stack, memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, a source layer contacting the vertical semiconductor channels, a backside isolation dielectric layer contacting a backside surface of the source layer, and a source power supply mesh including a planar portion of a source-side electrically conductive layer that is located on a backside of the backside isolation dielectric layer and electrically connected to the source layer by conductive material portions that extend through the backside isolation dielectric layer.

公开(公告)号：US11646081B2

公开(公告)日：2023-05-09

申请号：US17392500

申请日：2021-08-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Peter Rabkin ,  Henry Chin ,  Ken Oowada ,  Dengtao Zhao ,  Gerrit Jan Hemink

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  H01L27/11565 ,  H01L25/065 ,  H01L27/11582

CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/349 ,  H01L25/0657 ,  H01L27/11565 ,  H01L27/11582 ,  H01L2225/06562

Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

公开(公告)号：US11508654B2

公开(公告)日：2022-11-22

申请号：US16886702

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/115 ,  H01L27/06 ,  H01L23/00 ,  H01L49/02 ,  H01L27/11582

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

公开(公告)号：US11276705B2

公开(公告)日：2022-03-15

申请号：US16552089

申请日：2019-08-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L27/1158 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11514 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11529

Abstract: A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

公开(公告)号：US11094653B2

公开(公告)日：2021-08-17

申请号：US16682848

申请日：2019-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L23/52 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.

公开(公告)号：US10755788B2

公开(公告)日：2020-08-25

申请号：US16233780

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L27/1157 ,  H01L27/11524

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.

公开(公告)号：US11869877B2

公开(公告)日：2024-01-09

申请号：US17396291

申请日：2021-08-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L23/32 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/32 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/2101 ,  H01L2224/32146 ,  H01L2224/73267 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2924/37001

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.

公开(公告)号：US20230041476A1

公开(公告)日：2023-02-09

申请号：US17392500

申请日：2021-08-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Peter Rabkin ,  Henry Chin ,  Ken Oowada ,  Dengtao Zhao ,  Gerrit Jan Hemink

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

公开(公告)号：US11444016B2

公开(公告)日：2022-09-13

申请号：US16886695

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L27/115 ,  H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L27/11582

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

公开(公告)号：US11322509B2

公开(公告)日：2022-05-03

申请号：US17001270

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L21/8239 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10

Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.