Invention Grant
- Patent Title: Process for the manufacture of a semiconductor element comprising a layer for trapping charges
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Application No.: US15577133Application Date: 2016-06-01
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Publication No.: US10297464B2Publication Date: 2019-05-21
- Inventor: Marcel Broekaart , Luciana Capello , Isabelle Bertrand , Norbert Colombet
- Applicant: Soitec
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Priority: FR1555248 20150609
- International Application: PCT/EP2016/062334 WO 20160601
- International Announcement: WO2016/198298 WO 20161215
- Main IPC: H01L21/324
- IPC: H01L21/324 ; H01L21/322 ; H01L21/84 ; H01L21/66 ; H01L29/10 ; H01L21/762 ; H01L21/268 ; H01L21/67
Abstract:
A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1,100° C., for a period of time of at least 15 seconds.
Public/Granted literature
- US20180182640A1 PROCESS FOR THE MANUFACTURE OF A SEMICONDUCTOR ELEMENT COMPRISING A LAYER FOR TRAPPING CHARGES Public/Granted day:2018-06-28
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