公开(公告)号：US20220301847A1

公开(公告)日：2022-09-22

申请号：US17805206

申请日：2022-06-02

申请人： Soitec

发明人： Patrick Reynaud ,  Marcel Broekaart ,  Frédéric Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC分类号： H01L21/02 ,  H01L21/762

摘要： A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

公开(公告)号：US10510531B2

公开(公告)日：2019-12-17

申请号：US15803447

申请日：2017-11-03

申请人： Soitec

发明人： Oleg Kononchuk ,  Isabelle Bertrand ,  Luciana Capello ,  Marcel Broekaart

IPC分类号： H01L21/02 ,  H01L21/268 ,  H01L21/322 ,  H01L21/324 ,  C30B29/06 ,  H01L21/762 ,  H01L27/12

摘要： A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm·cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800° C. and 1250° C. and then cooled at a cooldown rate less than 5° C./second when the curing temperature is between 1250° C. and 1150° C., less than 20° C./second when the curing temperature is between 1150° C. and 1100° C., and less than 50° C./second when the curing temperature is between 1100° C. and 800° C.

公开(公告)号：US20230005787A1

公开(公告)日：2023-01-05

申请号：US17756244

申请日：2020-11-25

申请人： Soitec

发明人： Young-Pil Kim ,  Daniel Delprat ,  Luciana Capello ,  Isabelle Bertrand ,  Frédéric Allibert

IPC分类号： H01L21/762 ,  H01L23/66 ,  H01L27/12 ,  H01L21/02

摘要： A handle substrate for a composite structure comprises a base substrate including an epitaxial layer of silicon on a monocrystalline silicon wafer obtained by Czochralski pulling, a passivation layer on and in contact with the epitaxial layer of silicon, and a charge-trapping layer on and in contact with the passivation layer. The monocrystalline silicon wafer of the base substrate exhibits a resistivity of between 10 and 500 ohm·cm, while the epitaxial layer of silicon exhibits a resistivity of greater than 2000 ohm·cm and a thickness ranging from 2 to 100 microns. The passivation layer is amorphous or polycrystalline. A method is described for forming such a substrate.

公开(公告)号：US11373856B2

公开(公告)日：2022-06-28

申请号：US16476415

申请日：2018-01-11

申请人： Soitec

发明人： Patrick Reynaud ,  Marcel Broekaart ,  Frederic Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/762

摘要： A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

公开(公告)号：US20200020520A1

公开(公告)日：2020-01-16

申请号：US16476415

申请日：2018-01-11

申请人： Soitec

发明人： Patrick Reynaud ,  Marcel Broekaart ,  Frederic Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC分类号： H01L21/02 ,  H01L21/762

摘要： A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

公开(公告)号：US20180130698A1

公开(公告)日：2018-05-10

申请号：US15803447

申请日：2017-11-03

申请人： Soitec

发明人： Oleg Kononchuk ,  Isabelle Bertrand ,  Luciana Capello ,  Marcel Broekaart

IPC分类号： H01L21/762 ,  H01L21/324 ,  H01L27/12 ,  H01L21/02 ,  C30B29/06

CPC分类号： H01L21/02337 ,  C30B29/06 ,  H01L21/02002 ,  H01L21/02005 ,  H01L21/02008 ,  H01L21/02123 ,  H01L21/02255 ,  H01L21/02296 ,  H01L21/02381 ,  H01L21/2686 ,  H01L21/3226 ,  H01L21/324 ,  H01L21/76243 ,  H01L21/76251 ,  H01L21/76254 ,  H01L27/1203

摘要： A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm·cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800° C. and 1250° C. and then cooled at a cooldown rate less than 5° C./second when the curing temperature is between 1250° C. and 1150° C., less than 20° C./second when the curing temperature is between 1150° C. and 1100° C., and less than 50° C./second when the curing temperature is between 1100° C. and 800° C.

公开(公告)号：US20240120191A1

公开(公告)日：2024-04-11

申请号：US18263802

申请日：2022-02-14

申请人： Soitec

发明人： Isabelle Huyet ,  Luciana Capello

IPC分类号： H01L21/02

CPC分类号： H01L21/02032 ,  H01L21/02008

摘要： A method is used for preparing the residue of a donor substrate, the residue comprising, on a peripheral zone of a main face, a peripheral ring. The method comprises: a first step of removing at least part of the peripheral ring; a second step of processing the main face of the residue aiming to remove a surface layer; a third step, after the second step, of grinding the peripheral zone of the main face of the residue, the third grinding step aiming to reduce the elevation of the peripheral zone.

公开(公告)号：US10297464B2

公开(公告)日：2019-05-21

申请号：US15577133

申请日：2016-06-01

申请人： Soitec

发明人： Marcel Broekaart ,  Luciana Capello ,  Isabelle Bertrand ,  Norbert Colombet

IPC分类号： H01L21/324 ,  H01L21/322 ,  H01L21/84 ,  H01L21/66 ,  H01L29/10 ,  H01L21/762 ,  H01L21/268 ,  H01L21/67

摘要： A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1,100° C., for a period of time of at least 15 seconds.

公开(公告)号：US20180182640A1

公开(公告)日：2018-06-28

申请号：US15577133

申请日：2016-06-01

申请人： Soitec

发明人： Marcel Broekaart ,  Luciana Capello ,  Isabelle Bertrand ,  Norbert Colombet

IPC分类号： H01L21/324 ,  H01L21/322 ,  H01L29/10 ,  H01L21/84 ,  H01L21/66

CPC分类号： H01L21/324 ,  H01L21/2686 ,  H01L21/3226 ,  H01L21/67115 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/84 ,  H01L22/14 ,  H01L29/1079

摘要： A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1100° C., for a period of time of at least 15 seconds.