公开(公告)号：US20210050249A1

公开(公告)日：2021-02-18

申请号：US16969346

申请日：2019-01-14

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk ,  Nadia Ben Mohamed ,  Rénald Guerin ,  Norbert Colombet

IPC: H01L21/762

Abstract: A detachable structure comprises a carrier substrate and a silicon oxide layer positioned on the substrate at a first interface. The detachable structure is notable in that: the oxide layer has a thickness of less than 200 nm; light hydrogen and/or helium species are distributed deeply and over the entire area of the structure according to an implantation profile, a maximum concentration of which is located in the thickness of the oxide layer; the total dose of implanted light species, relative to the thickness of the oxide layer, exceeds, at least by a factor of five, the solubility limit of these light species in the oxide layer.

公开(公告)号：US11424156B2

公开(公告)日：2022-08-23

申请号：US16969346

申请日：2019-01-14

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk ,  Nadia Ben Mohamed ,  Rénald Guerin ,  Norbert Colombet

IPC: H01L21/762 ,  H01L21/20

Abstract: A detachable structure comprises a carrier substrate and a silicon oxide layer positioned on the substrate at a first interface. The detachable structure is notable in that: the oxide layer has a thickness of less than 200 nm; light hydrogen and/or helium species are distributed deeply and over the entire area of the structure according to an implantation profile, a maximum concentration of which is located in the thickness of the oxide layer; the total dose of implanted light species, relative to the thickness of the oxide layer, exceeds, at least by a factor of five, the solubility limit of these light species in the oxide layer.

公开(公告)号：US10297464B2

公开(公告)日：2019-05-21

申请号：US15577133

申请日：2016-06-01

Applicant: Soitec

Inventor： Marcel Broekaart ,  Luciana Capello ,  Isabelle Bertrand ,  Norbert Colombet

IPC: H01L21/324 ,  H01L21/322 ,  H01L21/84 ,  H01L21/66 ,  H01L29/10 ,  H01L21/762 ,  H01L21/268 ,  H01L21/67

Abstract: A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1,100° C., for a period of time of at least 15 seconds.

公开(公告)号：US20180182640A1

公开(公告)日：2018-06-28

申请号：US15577133

申请日：2016-06-01

Applicant: Soitec

Inventor： Marcel Broekaart ,  Luciana Capello ,  Isabelle Bertrand ,  Norbert Colombet

IPC: H01L21/324 ,  H01L21/322 ,  H01L29/10 ,  H01L21/84 ,  H01L21/66

CPC classification number: H01L21/324 ,  H01L21/2686 ,  H01L21/3226 ,  H01L21/67115 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/84 ,  H01L22/14 ,  H01L29/1079

Abstract: A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1100° C., for a period of time of at least 15 seconds.