Invention Grant
- Patent Title: Semiconductor device and method of forming PoP semiconductor device with RDL over top package
-
Application No.: US15676881Application Date: 2017-08-14
-
Publication No.: US10297519B2Publication Date: 2019-05-21
- Inventor: Yaojian Lin
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Brian M. Kaufman; Robert D. Atkins
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L25/00 ; H01L23/552 ; H01L23/00 ; H01L25/16 ; H01L23/538 ; H01L21/56 ; H01L25/10 ; H01L23/36 ; H01L23/13 ; H01L23/373 ; H01L23/498 ; H01L21/66 ; H01L25/065 ; H05K1/18 ; H05K3/28

Abstract:
A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.
Public/Granted literature
- US20180012857A1 Semiconductor Device and Method of Forming PoP Semiconductor Device with RDL Over Top Package Public/Granted day:2018-01-11
Information query
IPC分类: