Invention Grant
- Patent Title: Method of forming complementary nano-sheet/wire transistor devices with same depth contacts
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Application No.: US15898812Application Date: 2018-02-19
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Publication No.: US10304833B1Publication Date: 2019-05-28
- Inventor: Puneet Harischandra Suvarna , Bipul C. Paul , Ruilong Xie , Bartlomiej Jan Pawlak , Lars W. Liebmann , Daniel Chanemougame , Nicholas V. LiCausi , Andreas Knorr
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L29/775
- IPC: H01L29/775 ; H01L29/78 ; H01L27/092 ; H01L21/02 ; H01L21/8238 ; H01L29/06 ; H01L29/10 ; H01L29/423 ; H01L27/12
Abstract:
A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.
Information query
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